Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

OPTIMIZATION_MODE

Controls the Compiler's high-level optimization strategy. By default, the Quartus Prime Compiler optimizes in a balanced mode, targeting the design's timing constraints. The alternate modes cause the Compiler to prioritize a particular optimization metric. High effort modes primarily enable additional optimizations that increase compilation time. Superior and Aggressive modes may increase compilation time and also make trade-offs that may harm the other optimization metrics (performance, area, etc.).\r\n\r\n'High Performance Effort' mode will cause the compiler to target increased positive timing margin, increase the timing optimization effort applied during placement and routing, and enable timing-related Physical Synthesis optimizations (as allowed by the register optimization settings below). Each of these additional optimizations can increase compilation time. 'Superior Performance' mode enables the same optimizations as 'High Performance Effort' mode, and additionally enables options during Analysis & Synthesis to maximize design performance at a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting which could also negatively affect overall optimization quality. Modes with Maximum Placement Effort increase placement optimization effort by an additional amount.\r\n\r\n'High Routability Effort' modes guide Placement or Packing to spend additional compilation time reducing routing utilization, which can improve routability and also saves dynamic power. 'Optimize Netlist for Routability' mode makes netlist modifications to increase routability at the possible expense of performance. In 'Aggressive Power' mode, the Compiler will further target reducing the routing usage of signals with the highest specified (via Signal Activity File) or estimated toggle rates, saving additional dynamic power but potentially affecting performance.\r\n\r\n'Aggressive Area' mode instructs the Compiler to target an area minimal solution, even if this reduces overall timing performance.\r\n\r\n'Aggressive Compile Time' mode instructs the Compiler to reduce performance optimization effort and perform minimal reporting in order to save compile time.\r\n\r\n'Fast Functional Test' mode instructs the Compiler minimize setup-timing optimization effort in order to save compile time.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.

Type

Enumeration

Values

  • Aggressive Area
  • Aggressive Compile Time
  • Aggressive Power
  • Balanced
  • Fast Functional Test
  • High Packing Routability Effort
  • High Performance Effort
  • High Performance Effort with Maximum Placement Effort
  • High Performance with Aggressive Power Effort
  • High Placement Routability Effort
  • High Routability Effort
  • Optimize Netlist for Routability
  • Superior Performance
  • Superior Performance with Maximum Placement Effort

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Fitter report.

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name OPTIMIZATION_MODE <value>

Default Value

Balanced