Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_TIME_SCALE

Specifies the time unit used to represent timing delays in each Verilog Output File. The value for the Time Scale option may be between 0.001 ns and 10ns, and should be a multiple of 10.

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_TIME_SCALE -section_id <section identifier> <value>
set_global_assignment -name EDA_TIME_SCALE -entity <entity name> -section_id <section identifier> <value>