Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

DEFAULT_HOLD_MULTICYCLE

Determines the default hold multicycle. The 'Same as Multicycle' setting ensures that the signal is latched on the final edge only. The 'One' setting assumes that the design can latch on any edge, up to and including the final edge. The 'Same as Multicycle' setting will give fewer hold time violation warnings. The 'One' setting is more restrictive, but it is the default setting for the Timing Analyzer and other third-party timing analyzers. This setting can be overridden on specific nodes with the Hold Multicycle option.

Type

Enumeration

Values

  • One
  • Same as Multicycle

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

None

Syntax

set_global_assignment -name DEFAULT_HOLD_MULTICYCLE <value>

Default Value

Same as Multicycle

Example

set_global_assignment -name default_hold_multicycle "Same as Multicycle"
set_global_assignment -name default_hold_multicycle "One"

See Also

MULTICYCLE, SRC_MULTICYCLE, HOLD_MULTICYCLE, SRC_HOLD_MULTICYCLE, SETUP_RELATIONSHIP, HOLD_RELATIONSHIP