Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

INFER_RAMS_FROM_RAW_LOGIC

Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL patterns that differ from Intel FPGA RAM templates are initially converted into logic. However, these structures function as RAM and, because of that, the Compiler may create an altsyncram megafunction instance for them at a later stage when this assignment is on. With this assignment is turned on, the Compiler may use more device RAM resources and less LABs.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC <value>
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC -entity <entity name> <value>
set_instance_assignment -name INFER_RAMS_FROM_RAW_LOGIC -to <to> -entity <entity name> <value>

Default Value

On

Example

set_global_assignment -name infer_rams_from_raw_logic off
set_instance_assignment -name infer_rams_from_raw_logic off -to foo