Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

POWER_UP_LEVEL

Causes a register to power up with the specified logic level, either High (1) or Low (0). If this option is specified for an input pin, it is automatically transferred to the register that is driven by the pin if the following conditions are present: (1) there is no intervening logic, other than inversion, between the pin and the register; (2) the input pin drives the data input of the register; and (3) the input pin does not fan-out to any other logic. If this option is specified for an output or bidirectional pin, it is automatically transferred to the register that feeds the pin if: (1) there is no intervening logic, other than inversion, between the register and the pin; and (2) the register does not fan-out to any other logic. You can assign this option to any register, or to a pin with any logic configuration other than those described above. You can also assign this option to a design entity containing registers if you want to set the power level for all registers in the design entity. In order for the register to power up with the specified logic level, the Compiler may perform NOT Gate Push-Back on the register.

Type

Enumeration

Values

  • High
  • Low

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name POWER_UP_LEVEL -entity <entity name> <value>
set_instance_assignment -name POWER_UP_LEVEL -to <to> -entity <entity name> <value>

Example

set_instance_assignment -name power_up_level low -to foo

See Also

Power-Up Don't Care