Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

REMOVE_REDUNDANT_LOGIC_CELLS

Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.

Type

Boolean

Device Support

  • Intel Agilex® 5
  • Intel Agilex® 7
  • Arria® 10
  • Cyclone® 10 GX
  • Stratix® 10

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <entity name> <value>
set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to <to> -entity <entity name> <value>
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <value>

Default Value

Off

Example

set_global_assignment -name remove_redundant_logic_cells on
set_instance_assignment -name remove_redundant_logic_cells on -to node