Visible to Intel only — GUID: tgq1684429761293
Ixiasoft
Visible to Intel only — GUID: tgq1684429761293
Ixiasoft
2.4.1. RTL Simulation
Simulation allows you to verify the design behavior before configuring the FPGA device with the verified design. You can specify input vectors to your simulator and then the simulator determines and reports the expected corresponding outputs during the run time you specify.
The Intel FPGA simulation process involves setting up your supported simulator working environment, compiling simulation model libraries, generating simulation files, running your simulator, and interpreting the results.
The Quartus® Prime software does not include a native simulator but provides support for the specific RTL- and gate-level EDA simulators.
For more information on how to perform design simulations, refer to the following documents:
- Questa* Intel® FPGA Edition Quick-Start: Quartus® Prime Pro Edition
- Quartus® Prime Pro Edition User Guide: Third-party Simulation
- Embedded Peripherals IP User Guide