Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813741
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Agilex™ 5 Device Design Guidelines 2. System Specification 3. Device Selection 4. Design Entry 5. Board and Software consideration 6. Design Implementation, Analysis, Optimization and Verification 7. Debugging
1. Introduction to Agilex™ 5 Device Design Guidelines x
1.1. Introduction to Agilex™ 5 Device Design Guide Revision History
2. System Specification x
2.1. Design Specification 2.2. Install Quartus® Prime Software 2.3. IP selection 2.4. Simulation 2.5. Preparing for Design Entry 2.6. I/O Summary 2.7. Using SDM in your devices 2.8. System Specification Revision History
2.3. IP selection x
2.3.1. IP cores 2.3.2. HPS IP
2.3.1. IP cores x
2.3.1.1. Interface Protocol IP cores
2.4. Simulation x
2.4.1. RTL Simulation 2.4.2. Simics® Simulator
2.5. Preparing for Design Entry x
2.5.1. Coding Styles and Design Recommendation 2.5.2. Platform Designer
3. Device Selection x
3.1. Device Variant 3.2. Device Selection Revision History
3.1. Device Variant x
3.1.1. Speed Grade and Package 3.1.2. Power option 3.1.3. Device Migration within Agilex™ 5 3.1.4. PLL 3.1.5. Logic element, Embedded memory, and DSP 3.1.6. I/O and LVDS SERDES 3.1.7. MIPI D-DPHY 3.1.8. Transceiver 3.1.9. Hard Processor System
4. Design Entry x
4.1. Design entry for FPGA 4.2. Design entry for Nios® V 4.3. Design entry for HPS 4.4. Design Entry Revision History
4.1. Design entry for FPGA x
4.1.1. Configuration Consideration 4.1.2. I/O and LVDS SERDES 4.1.3. PLL and Clock Planning 4.1.4. EMIF 4.1.5. Transceiver Planning 4.1.6. Sensors 4.1.7. MIPI D-PHY
4.1.1. Configuration Consideration x
4.1.1.1. Partial Reconfiguration 4.1.1.2. SEU
4.1.2. I/O and LVDS SERDES x
4.1.2.1. Making FPGA Pin Assignments Checklist 4.1.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device 4.1.2.3. Agilex™ 5 I/O Features and Pin Connections
4.1.2.3. Agilex™ 5 I/O Features and Pin Connections x
4.1.2.3.1. I/O Signaling Type 4.1.2.3.2. Selectable Standards and Flexible I/O Banks 4.1.2.3.3. Agilex™ 5 Dual-Purpose and Special Pin Connections 4.1.2.3.4. Agilex™ 5 I/O Features
4.1.3. PLL and Clock Planning x
4.1.3.1. Clock and PLL Selection 4.1.3.2. PLL Feature Guidelines 4.1.3.3. Clock Feedback Mode 4.1.3.4. Clock Outputs 4.1.3.5. Clock Control Features
4.1.6. Sensors x
4.1.6.1. Voltage sensor 4.1.6.2. Temperature Sensor and Temperature Diode
4.3. Design entry for HPS x
4.3.1. Simics® Simulator 4.3.2. HPS IP Instantiation in Quartus® Prime
5. Board and Software consideration x
5.1. Early Board Planning 5.2. Boundary Scan for FPGA and HPS 5.3. Pin Connection Considerations for Board Design 5.4. Planning for Device Configuration 5.5. Board and Software Consideration Revision History
5.1. Early Board Planning x
5.1.1. Power - SmartVID or Fix Voltage 5.1.2. Thermal Management and Design
5.1.1. Power - SmartVID or Fix Voltage x
5.1.1.1. Intel® FPGA Power and Thermal Calculator 5.1.1.2. Power-Up and Power-Down Sequencing
5.3. Pin Connection Considerations for Board Design x
5.3.1. Board-Related Quartus® Prime Settings 5.3.2. Signal Integrity Considerations 5.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
5.3.1. Board-Related Quartus® Prime Settings x
5.3.1.1. Unused Pins
5.3.2. Signal Integrity Considerations x
5.3.2.1. High-Speed Board Design 5.3.2.2. Simultaneous Switching Noise 5.3.2.3. I/O Termination
5.4. Planning for Device Configuration x
5.4.1. Device Power Cycling and Reconfiguration 5.4.2. Configuration Scheme Selection 5.4.3. Configuration Features 5.4.4. Quartus® Prime Configuration Settings 5.4.5. Configuration Pin Connections 5.4.6. JTAG Pins 5.4.7. MSEL Configuration Mode Pins 5.4.8. Other Configuration Pins
5.4.2. Configuration Scheme Selection x
5.4.2.1. Serial Configuration Devices 5.4.2.2. Intel® FPGA Download Cable II
5.4.4. Quartus® Prime Configuration Settings x
5.4.4.1. Optional Configuration Pins 5.4.4.2. Dual Purpose Configuration Pins
5.4.5. Configuration Pin Connections x
5.4.5.1. Configuration Pin Voltage Level 5.4.5.2. Clock Trace Signal Integrity
5.4.6. JTAG Pins x
5.4.6.1. JTAG Pin Connections 5.4.6.2. JTAG Signal Buffering 5.4.6.3. Download Cable Operating Voltage
6. Design Implementation, Analysis, Optimization and Verification x
6.1. Synthesis Tool 6.2. Device Resource Reports 6.3. Quartus® Prime Message 6.4. Design Assistant Design Rule Checking 6.5. Timing Constraints and Analysis 6.6. Area and Timing Optimization 6.7. Preserving Performance and Reducing Compilation Time 6.8. Designing with Hyperflex® 6.9. Simulation 6.10. Power Analysis 6.11. Design Implementation, Analysis, Optimization and Verification Revision History
6.5. Timing Constraints and Analysis x
6.5.1. Recommended Timing Optimization and Analysis Assignments 6.5.2. SDC-on-RTL and Post-Synthesis Static Timing Analysis
7. Debugging x
7.1. On-Chip Debug Overview 7.2. On-Chip Debugging Tools 7.3. Debugging Revision History
1. Introduction to Agilex™ 5 Device Design Guidelines
2. System Specification
3. Device Selection
4. Design Entry
5. Board and Software consideration
6. Design Implementation, Analysis, Optimization and Verification
7. Debugging

4.1.4. EMIF

This section describes the EMIF design considerations for the FPGA.

Table 25.  Memory Interfaces Checklist

Number

Done ?

Checklist Item

1

  

Use External Memory Interfaces (EMIF) IP for each memory interface, and follow connection guidelines and restrictions in External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs .

2

  

The Agilex™ 5 E-Series Devices can only support component interface. Agilex™ 5 D-Series Devices can support both DIMM and component interface.

3

  

The Agilex™ 5 D-Series and E-Series Devices can support up to 2 ranks only.

4

  

You can only implement EMIF on HSIO bank. EMIF is not supported on HVIO bank.

5

  

The EMIF controller user interface in Agilex™ 5 Series Devices uses the AXI protocol.

Agilex™ 5 devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks. The Agilex™ 5 FPGA can support DDR external memory on any HSIO banks. The self-calibrating External Memory Interfaces IP core is optimized to take advantage of the I/O structure in HSIO bank. The External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel memory controller Intel® FPGA IP functions, the External Memory Interfaces IP core is instantiated automatically. If you design multiple memory interfaces into the device using Intel® FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

Agilex™ 5 EMIF only supports fixed byte-lane arrangement. Within an I/O bank, only specific lanes can be used as Address/Command lane, and specific lanes can be used as Data Group. Within a Data Lane, the data strobe DQS and data DQ pin locations are fixed. Before you design your device pin-out, refer to pin mapping in the Product Architecture section in the External Memory Interfaces Agilex™ 5 FPGA IP User Guide for details and important restrictions related to the connections for these and other memory-related signals. You can implement a protocol that is not supported by External Memory Interfaces IP core by using the PHY Lite for Parallel Interfaces Intel® FPGA IP core.

Address and command pins within the address/command bank must follow a fixed pin-out scheme. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.

Table 26.  Restrictions for FPGA EMIF Pin Checklist

Number

Done?

Checklist Item

1

  

The Agilex™ 5 Series EMIF only supports fixed byte-lane arrangement. Only specific lanes can be used as Address/Command lane, and specific lanes can be used as Data Group. For information about pin mapping, refer to External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs .

2

  

Arbitrary placement of data mask pins within a data lane is not permitted. Pin index 6 must be used as data mask pin in DM/RDI/WDI is enabled

3

  

EMIF only supports 1.05V/1.1V/1.2V True Differential Signaling for PLL reference clock. Intel recommends that every EMIF interface to have its own PLL reference clock source. You must use I/O standard that has the same VCCIO_PIO requirement for the I/O standard used by the EMIF protocol. For more information about VCCIO_PIO, VID and VICM(DC) for each True Differential I/O standard, refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet.

4

  

Every EMIF interface must have its own RZQ pin and must be placed at Pin Index 2, Lane 2 in the Address/Command Lanes.

5

  

Intel recommends that you use the Quartus® Prime software to verify that your EMIF pin assignment is correct by compiling the EMIF example design.

The guidelines in the "Recommended Board Guideline for Initial Board Bring up Checklist" table ensure the board is designed with adequate margin and allow easy probing of critical signals and stability of voltage rails during debug. Ability to change the reference clock frequency allows you to test the interface for multiple operating frequency. If the interface works at a lower speed, the interface is correctly pinned out and functional.

Table 27.  Recommended Board Guideline for Initial Board Bring up Checklist

Number

Done?

Checklist Item

1

  

Perform board simulation to confirm adequate margin on Address/Command and Data Path.

2

  

Have probe points for voltage rails, Address/Command signals and one data lane.

3

  

Use a programmable reference clock generator for EMIF reference clock source to support multiple frequency.

4

  

If you are using DIMM (only supported on Agilex™ 5 D-Series devices), connect every signal from FPGA to DIMM even if the design does not use it (for example: wider address width, all CS/CKE/ODT signals).

5

  

Leave adequate clearance for socket/cooling solution, and logic analyzer interfaces on the DIMM.

6

  

Use the EMIF example design generated by Quartus® Prime Software to perform the initial bring up.

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