Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

5.4.4.2. Dual Purpose Configuration Pins

Table 52.  Dual Purpose Configuration Pins Checklist
Number Done? Checklist Item
1   Plan the dual purpose pins that can function as configuration pins and user I/O pins.

In designs that do not include the HPS, the below configuration pins used for the Avalon® streaming interface ×16 configuration schemes can optionally be used as user I/O pins after the configuration has been completed. Enable the pins to function as dual purpose pins in the Quartus® Prime software prior to compilation, if desired.

  • AVST_CLK
  • AVST_VALID
  • AVST_DATA[15:0]
Table 53.  Dual-Purpose Pin Restrictions for Avalon® streaming interfacex16 Configuration Scheme
Dual-Purpose Pin Avalon® streaming interface x16
Not Used in User Mode Used in User Mode
AVST_CLK Setting: As input tri-stated Setting: Set as regular I/O

Pin Connection: Set as Input and assign ALL pins in pin assignment

AVST_VALID
AVST_DATA[15:0]
Note: All pins in the same group name must be assigned to the physical pin in pin assignment. For instance, if only 2 out of 16 pins from AVST_DATA[15:0] are used, then all 16 pins must be assigned to physical pins including the unused pins in the user design.
Note: All pins with pin assignments must be in known state, whether weak pull-up or weak pull-down.
Note: AVSTx16 configuration scheme cannot be used in designs that include the HPS.