Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

5.4.1. Device Power Cycling and Reconfiguration

Table 44.  Device Power Cycling and Reconfiguration Checklist
Number Done? Checklist Item
1   Consider designing your system to support power cycling the device to ensure error recovery under all reconfiguration circumstances.

Unlike previous FPGA devices that used state machines for controlling configuration, the Agilex™ 5 devices use the triple-redundant processors in the SDM to control configuration. To ensure error recovery under all reconfiguration circumstances, Intel® recommends that you design your system to support power cycling the device if needed. In almost all use cases, asserting nCONFIG provides adequate error recovery, however, a power cycle may be required in rare instances. A power cycle completely re-initializes the device, samples MSEL, reads the fuses and runs the SDM BootROM code. Device power up and power down sequences must be followed during the power cycle.