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5.1. Understanding the Design Steps for CvP Initialization Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode
5.4. Bringing Up the Hardware
5.5. CvP Debugging Check List
5.6. Known Issues and Solutions
5.2.1. Downloading and Generating the High Performance Reference Design
5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region
5.2.4. Setting up CvP Parameters for CvP Initialization Mode
5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow
5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3.1. Downloading and Generating the High Performance Reference Design
5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region
5.3.4. Setting up CvP Parameters for CvP Update Mode
5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
5.3.6. Compiling the Design for the CvP Update Mode
5.3.7. Splitting the SOF File for the CvP Update Design Mode
5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
6.3.1. Altera-defined Vendor Specific Capability Header Register
6.3.2. Altera-defined Vendor Specific Header Register
6.3.3. Altera Marker Register
6.3.4. CvP Status Register
6.3.5. CvP Mode Control Register
6.3.6. CvP Data Registers
6.3.7. CvP Programming Control Register
6.3.8. Uncorrectable Internal Error Status Register
6.3.9. Uncorrectable Internal Error Mask Register
6.3.10. Correctable Internal Error Status Register
6.3.11. Correctable Internal Error Mask Register
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5.6.1. Using MSI-X in CvP Initialization Mode
If you are using message signaled interrupts (MSI-X) in CvP Initialization mode, you must ensure that the MSI-X table loads after the Quartus Prime software loads the core image.
To ensure that MSI-X tables are set up correctly, follow the steps below:
- Set up the MSI-X in the Quartus Prime software and enable MSI-X.
- Load the periphery image.
- Load the core image.
- If a driver was set up previously, uninstall and reinstall the driver using your application software after the quartus_cvp core image has been loaded. Or, disable and re-enable the driver after the quartus_cvp core image has been loaded.
- The MSI-X table is set up. You can now observe interrupts on the link.