Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

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ID 683889
Date 9/04/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FPGA Configuration using CvP 3. CvP Topologies 4. Design Considerations 5. CvP Example Designs 6. CvP Driver and Registers 7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes 1.4. CvP Revision Design Flow 1.5. CvP Topologies 1.6. Additional Information about PCI Express
2. FPGA Configuration using CvP x
2.1. CvP Configuration Images 2.2. CvP Modes 2.3. Alternative to CvP Initialization: Autonomous HIP Mode 2.4. CvP Compression and Encryption Features 2.5. Core Image Update 2.6. CvP Pins
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
2.4. CvP Compression and Encryption Features x
2.4.1. Data Compression 2.4.2. Data Encryption
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints 3.3. Mixed Chain
3.3. Mixed Chain x
3.3.1. Configuring Slave FPGAs with Different Configuration Files 3.3.2. Configuring Slave FPGAs with a Single Configuration File
4. Design Considerations x
4.1. Preparing the Design for CvP Revision Design Flow 4.2. Designing CvP for an Open System 4.3. Designing CvP for a Closed System 4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller
4.2. Designing CvP for an Open System x
4.2.1. FPGA Power Supplies Ramp Time Requirement 4.2.2. PCIe Wake-Up Time Requirement
4.2.2. PCIe Wake-Up Time Requirement x
4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode 4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode
4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode x
4.2.2.2.1. Recommended Configuration Schemes 4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement
5. CvP Example Designs x
5.1. Understanding the Design Steps for CvP Initialization Mode 5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5.3. Understanding the Design Steps for CvP Update Mode 5.4. Bringing Up the Hardware 5.5. CvP Debugging Check List 5.6. Known Issues and Solutions
5.1. Understanding the Design Steps for CvP Initialization Mode x
5.1.1. Downloading and Generating the High Performance Reference Design 5.1.2. Setting up CvP Parameters for CvP Initialization Mode 5.1.3. Compiling the Design for the CvP Initialization Mode 5.1.4. Splitting the SOF File for the CvP Initialization Design Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow x
5.2.1. Downloading and Generating the High Performance Reference Design 5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.2.4. Setting up CvP Parameters for CvP Initialization Mode 5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow 5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode x
5.3.1. Downloading and Generating the High Performance Reference Design 5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.3.4. Setting up CvP Parameters for CvP Update Mode 5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.3.6. Compiling the Design for the CvP Update Mode 5.3.7. Splitting the SOF File for the CvP Update Design Mode 5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
5.4. Bringing Up the Hardware x
5.4.1. Installing Jungo WinDriver in Windows Systems 5.4.2. Installing Jungo WinDriver in Linux Systems 5.4.3. Installing Open Source CvP Driver in Linux System 5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit 5.4.5. Programming CvP Images and Validating the Link
5.6. Known Issues and Solutions x
5.6.1. Using MSI-X in CvP Initialization Mode
6. CvP Driver and Registers x
6.1. CvP Driver Support 6.2. CvP Driver Flow 6.3. VSEC Registers for CvP
6.3. VSEC Registers for CvP x
6.3.1. Altera-defined Vendor Specific Capability Header Register 6.3.2. Altera-defined Vendor Specific Header Register 6.3.3. Altera Marker Register 6.3.4. CvP Status Register 6.3.5. CvP Mode Control Register 6.3.6. CvP Data Registers 6.3.7. CvP Programming Control Register 6.3.8. Uncorrectable Internal Error Status Register 6.3.9. Uncorrectable Internal Error Mask Register 6.3.10. Correctable Internal Error Status Register 6.3.11. Correctable Internal Error Mask Register
1. Overview
2. FPGA Configuration using CvP
3. CvP Topologies
4. Design Considerations
5. CvP Example Designs
6. CvP Driver and Registers
7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

Document Version Changes
2020.09.04
  • Added information about custom CvP driver for Linux in section Bringing Up the Hardware.
  • Added a note about the availability of Jungo WinDriver in following sections:
    • Bringing Up the Hardware
    • CvP Driver Support
  • Added new section Installing Open Source CvP Driver in Linux System.
  • Added steps to program the core image using the open source Linux diver in section Programming CvP Images.
Date Version Changes
October 2016 2.0
  • Changed the document title to Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide.
  • Added references to the Configuration Timing Waveforms.
  • Corrected the PCIe Timing Sequence diagrams for both CvP initialization and update mode.
  • Added multiple snapshots of the Intel® Quartus® Prime Standard Edition illustrating the following design steps:
    • Downloading and Generating the High Performance Reference Design
    • Setting up CvP Parameters for CvP Initialization Mode
    • Setting up CvP Parameters for CvP Update Mode
  • Simplified the Figure: Switch 4 (SW4) Configuration for MSEL[4:0] =5’b10010 on the back view of Stratix V Device Kit.
  • Added the timeout value for CvP_CONFIG_READY in the Figure: CvP Driver Flow.
  • Fixed assorted typos and formatting issues.
May 2016 1.9
  • Corrected the nPERST pin locations for Cyclone V devices in the Table: CvP pin descriptions and connection guidelines.
  • Added the pin descriptions for INIT_DONE and CONF_DONE.
  • Corrected the values of CvP Mode Control Register in the Table: CvP Mode Control Register (Byte Offset: 0x220).
  • Clarified the Bit[5] as CVP_CONFIG_ERROR_LATCHED bit in the Table: Uncorrectable Internal Error Status Register (Byte Offset: 0x234).
  • Removed references to Arria 10 devices. For CvP implementation in Arria 10 devices, refer to the Arria 10 CvP Initialization and Partial Reconfiguration over Protocol User Guide.
  • Fixed assorted typos and formatting issues.
November 2015 1.8
  • Updated the Table: CvP Support for Device Families.
  • Clarified the pin descriptions in the Table: CvP pin descriptions and connection guidelines.
  • Updated the example design reference to PCIe AVST and On-Chip Memory Interface design files.
  • Changed instances of Quartus II to Quartus Prime.
  • Removed the Daisy chain topology section.
December 2014 1.7
  • Updated the CvP Modes section to indicate difference between CvP Initialization and CvP Update modes.
  • Added Table: CvP Support for Device Families in the CvP Modes section.
  • Added a new section called Autonomous Mode.
  • Corrected a typographical error in Figure: "Switch 4 (SW4) Configuration for MSEL[4:0] =5’b10010 on the back view of Stratix V Device Kit" to indicate that down position signifies logic one.
  • Corrected modes supported for Arria V and Cyclone V Gen2 variants. Gen2 supports CvP initialization mode. Gen2 does not support CvP update mode.
  • Updated the Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller section dynamic reconfiguration usage guidelines.
  • Added a new section called Using MSI-X in CvP Initialization Mode under Known Issues and Solutions.
November 2013 1.6
  • Added optional CVP_DATA2 register for use when configuration data is 64 bits wide.
  • Added design constraint for input reference clock when more than one Transceiver Reconfiguration Controller connects to the transceivers on one side of the device.
  • Corrected errors in software driver flow diagram.
  • Added clarification that you must select either CvP Initialization mode or CvP Update mode. The two modes cannot be combined.
  • Updated CvP Pins section.
  • Updated CvP Example Designs chapter.
  • Updated CvP Features section in Design Considerations chapter.
August 2013 1.5
  • Added support for 64-bit data.
  • Changed supported clock frequencies for CvP updates using encrypted data and a non-volatile key. Only 12.5 MHz is supported.
  • Added reasons for using a compressed bitstream.
  • Clarified process to create separate design hierarchy for periphery and core logic.
  • Added table showing supported features in CvP Initialization and Update Mode and CvP Update Mode.
  • Clarified use of dummy writes for CvP driver in the teardown flow.
May 2013 1.4
  • Added CvP Example Designs.
  • Added Partitioning a Design for the CvP Design Flow section.
  • Updated the Power Supplies Ramp-Up Time and POR, PCIe Timing Sequence in CvP Initialization Mode, and PCIe Timing Sequence in CvP Update Mode figures.
  • Moved all links in all topics to the Related Information section for easy reference.
December 2012 1.3
  • Removed Gen 3 support from the CvP Update Mode in Table 2-1.
  • Added Table 5-3 to include the supported clock source for encrypted configuration data in CvP mode.
  • Added Table 6-2 to include the quartus_cvp command for compression and encryption modes.
  • Added Table 6-3 to include the CVP_NUMCLKS settings.
  • Updated Bit 1 and Bit 0 to reserved bits in Table 6-8.
  • Updated the CVP_NUMCLKS settings in Figure 6-1.
July 2012 1.2
  • Updated "Data Compression" and Data Encryption" sections.
  • Moved Table 5-6. Uncompressed .rbf sizes to Stratix V, Arria V, and Cyclone V Configuration, Design Security, and Remote System Upgrades chapters.
  • Added Jungo WinDriver and the Linux-based Plain Text C CvP driver in "Software Support" chapter.
  • Updated CVP_NUMCLKS byte settings in Table 6-8 and Figure 6-1.
January 2012 1.1
  • Added Arria V and Cyclone V devices.
  • Removed references to the CvP Off mode.
  • Updated Chapter 6, Software Support with PCIe driver and CvP programming information.
  • Added "Generating Periphery Image and Fabric Image" and "VSEC for CvP" sections.
May 2011 1.0 Initial release.
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