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Visible to Intel only — GUID: nik1412546917312
Ixiasoft
5.3. Understanding the Design Steps for CvP Update Mode
CvP update mode divides the design into periphery and core images (as the previous modes). Initially, you program the entire image (both periphery and core) using conventional programming options. Subsequently, you can download alternative versions of the core image using the PCI Express link.
You specify this mode in the Quartus Prime software by selecting the CvP Setting Core update. The following figure provides the high-level steps for CvP update mode.
- Downloading and Generating the High Performance Reference Design
- Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
- Creating an Alternate user_led.v File for the Reconfigurable Core Region
- Setting up CvP Parameters for CvP Update Mode
- Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
- Compiling the Design for the CvP Update Mode
- Splitting the SOF File for the CvP Update Design Mode
- Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
- Bringing Up the Hardware
By default, once the FPGA enters user mode, you can only reprogram the original static core image. If you want to have multiple core images in user mode, you can use the CvP Revision Design Flow to create multiple core images that connect to the same periphery image.
Section Content
Downloading and Generating the High Performance Reference Design
Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
Creating an Alternate user_led.v File for the Reconfigurable Core Region
Setting up CvP Parameters for CvP Update Mode
Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
Compiling the Design for the CvP Update Mode
Splitting the SOF File for the CvP Update Design Mode
Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow