Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.3. Understanding the Design Steps for CvP Update Mode

CvP update mode divides the design into periphery and core images (as the previous modes). Initially, you program the entire image (both periphery and core) using conventional programming options. Subsequently, you can download alternative versions of the core image using the PCI Express link.

You specify this mode in the Quartus Prime software by selecting the CvP Setting Core update. The following figure provides the high-level steps for CvP update mode.

Figure 35. Design Flow for CvP Update Mode
Note: When you select CvP update mode, you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP.

By default, once the FPGA enters user mode, you can only reprogram the original static core image. If you want to have multiple core images in user mode, you can use the CvP Revision Design Flow to create multiple core images that connect to the same periphery image.