Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

Download PDF
ID 683889
Date 9/04/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FPGA Configuration using CvP 3. CvP Topologies 4. Design Considerations 5. CvP Example Designs 6. CvP Driver and Registers 7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes 1.4. CvP Revision Design Flow 1.5. CvP Topologies 1.6. Additional Information about PCI Express
2. FPGA Configuration using CvP x
2.1. CvP Configuration Images 2.2. CvP Modes 2.3. Alternative to CvP Initialization: Autonomous HIP Mode 2.4. CvP Compression and Encryption Features 2.5. Core Image Update 2.6. CvP Pins
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
2.4. CvP Compression and Encryption Features x
2.4.1. Data Compression 2.4.2. Data Encryption
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints 3.3. Mixed Chain
3.3. Mixed Chain x
3.3.1. Configuring Slave FPGAs with Different Configuration Files 3.3.2. Configuring Slave FPGAs with a Single Configuration File
4. Design Considerations x
4.1. Preparing the Design for CvP Revision Design Flow 4.2. Designing CvP for an Open System 4.3. Designing CvP for a Closed System 4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller
4.2. Designing CvP for an Open System x
4.2.1. FPGA Power Supplies Ramp Time Requirement 4.2.2. PCIe Wake-Up Time Requirement
4.2.2. PCIe Wake-Up Time Requirement x
4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode 4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode
4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode x
4.2.2.2.1. Recommended Configuration Schemes 4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement
5. CvP Example Designs x
5.1. Understanding the Design Steps for CvP Initialization Mode 5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5.3. Understanding the Design Steps for CvP Update Mode 5.4. Bringing Up the Hardware 5.5. CvP Debugging Check List 5.6. Known Issues and Solutions
5.1. Understanding the Design Steps for CvP Initialization Mode x
5.1.1. Downloading and Generating the High Performance Reference Design 5.1.2. Setting up CvP Parameters for CvP Initialization Mode 5.1.3. Compiling the Design for the CvP Initialization Mode 5.1.4. Splitting the SOF File for the CvP Initialization Design Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow x
5.2.1. Downloading and Generating the High Performance Reference Design 5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.2.4. Setting up CvP Parameters for CvP Initialization Mode 5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow 5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode x
5.3.1. Downloading and Generating the High Performance Reference Design 5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.3.4. Setting up CvP Parameters for CvP Update Mode 5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.3.6. Compiling the Design for the CvP Update Mode 5.3.7. Splitting the SOF File for the CvP Update Design Mode 5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
5.4. Bringing Up the Hardware x
5.4.1. Installing Jungo WinDriver in Windows Systems 5.4.2. Installing Jungo WinDriver in Linux Systems 5.4.3. Installing Open Source CvP Driver in Linux System 5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit 5.4.5. Programming CvP Images and Validating the Link
5.6. Known Issues and Solutions x
5.6.1. Using MSI-X in CvP Initialization Mode
6. CvP Driver and Registers x
6.1. CvP Driver Support 6.2. CvP Driver Flow 6.3. VSEC Registers for CvP
6.3. VSEC Registers for CvP x
6.3.1. Altera-defined Vendor Specific Capability Header Register 6.3.2. Altera-defined Vendor Specific Header Register 6.3.3. Altera Marker Register 6.3.4. CvP Status Register 6.3.5. CvP Mode Control Register 6.3.6. CvP Data Registers 6.3.7. CvP Programming Control Register 6.3.8. Uncorrectable Internal Error Status Register 6.3.9. Uncorrectable Internal Error Mask Register 6.3.10. Correctable Internal Error Status Register 6.3.11. Correctable Internal Error Mask Register
1. Overview
2. FPGA Configuration using CvP
3. CvP Topologies
4. Design Considerations
5. CvP Example Designs
6. CvP Driver and Registers
7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

5.4.5. Programming CvP Images and Validating the Link

For CvP initialization mode, you must load the periphery image (top.periph.jic) and then download the core image core image (top.core.rbf) using the PCIe Link. You can use JTAG to load different programming files (i.e. .sof/.jic/periph.pof) into your selected CvP initialization enabled Stratix® V, Cyclone® V , or Arria® V device.

After loading the periphery image via the JTAG port, the link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Then, you can update the core image (top.core.rbf) using the quartus_cvp command over the PCIe link.

For CvP update mode, you first program the FPGA using the .sof or .pof image. After the programming completes the FPGA enters user mode. You can now reconfigure the core image ( .core.rbf), the quartus_cvp command or your own driver.

Follow these steps to program and test the CvP functionality:
  1. Plug in the Stratix V GX FPGA Development Kit to the PCI Express slot of the DUT PC and power it on. Altera recommends that you use the external power supply that the development kit includes.
  2. On the host PC, open the Quartus Prime Tools menu and select Programmer. The Programmer appears.
    Figure 50.  Quartus Prime Programmer Settings
  3. Click Auto Detect to verify that the USB Blaster recognizes the Stratix V FPGA.
  4. Follow these steps to program the periphery image:
    1. Select Stratix V device, then right click None under File column.
    2. Navigate to pcie_quartus_files/top.periph.jic and click Open.
    3. Under Program/Configure column, select 5SGXEA7K2 and EPCQ256.
    4. Click Start to program the periphery image to EPCQ256 flash.
  5. To force the host PC to re-enumerate the link with the new image, reboot/power cycle the DUT PC.
  6. You can use RW Utilities or another system software driver to verify the link status. The following figure shows that the RW Utilities enumeration includes an Altera PCIe on Bus 01.
    Figure 51. RW Everything Transcript
  7. You can also confirm expected link speed and width. For this Gen1 x1 example design, the following figure shows that both Altera EP Link Capability Register at 0x8C and Link Status register at 0x92 have value 0x11, which confirms the link successfully comes up as Gen1 x1.
    Figure 52. Checking Link Status
  8. Follow these steps to program the core image (top.core.rbf) into the FPGA:
    1. Open a DOS command window.
    2. Change to appropriate Quartus Prime bin install directory. Both 64-bit and 32-bit bin directories are available. This example uses C:\altera\13.0 \quartus\bin64.
    3. Type the following command to program the core image. The value of Vendor ID (vid) and Device ID (vid) are in hexadecimal and must match the values you specified on the Device Identification Registers tab of the Stratix V Hard IP for PCI Express IP Core GUI :
      quartus_cvp --vid=1172 --did=e001 <path>/top.core.rbf
    4. The figure below shows the results of successful CvP programming.
      Figure 53. Transcript from quartus_cvp Command
    If you implement your own software driver to program the core image, refer to the CvP Driver Support section in Chapter 6 of CvP User Guide.
    If you are using the OpenSource Linux driver, perform the following steps to program the core image:
    1. Copy the .core.rbf file to your working directory.
    2. Open a console in Linux. Change directory to the same mentioned above where the file is copied.
    3. Program the core image by typing the following command:
      cp *.core.rbf /dev/altera_cvp
You are now ready to run your own tests.
Related Information
Level Two Title