Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

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ID 683889
Date 9/04/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FPGA Configuration using CvP 3. CvP Topologies 4. Design Considerations 5. CvP Example Designs 6. CvP Driver and Registers 7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes 1.4. CvP Revision Design Flow 1.5. CvP Topologies 1.6. Additional Information about PCI Express
2. FPGA Configuration using CvP x
2.1. CvP Configuration Images 2.2. CvP Modes 2.3. Alternative to CvP Initialization: Autonomous HIP Mode 2.4. CvP Compression and Encryption Features 2.5. Core Image Update 2.6. CvP Pins
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
2.4. CvP Compression and Encryption Features x
2.4.1. Data Compression 2.4.2. Data Encryption
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints 3.3. Mixed Chain
3.3. Mixed Chain x
3.3.1. Configuring Slave FPGAs with Different Configuration Files 3.3.2. Configuring Slave FPGAs with a Single Configuration File
4. Design Considerations x
4.1. Preparing the Design for CvP Revision Design Flow 4.2. Designing CvP for an Open System 4.3. Designing CvP for a Closed System 4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller
4.2. Designing CvP for an Open System x
4.2.1. FPGA Power Supplies Ramp Time Requirement 4.2.2. PCIe Wake-Up Time Requirement
4.2.2. PCIe Wake-Up Time Requirement x
4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode 4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode
4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode x
4.2.2.2.1. Recommended Configuration Schemes 4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement
5. CvP Example Designs x
5.1. Understanding the Design Steps for CvP Initialization Mode 5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5.3. Understanding the Design Steps for CvP Update Mode 5.4. Bringing Up the Hardware 5.5. CvP Debugging Check List 5.6. Known Issues and Solutions
5.1. Understanding the Design Steps for CvP Initialization Mode x
5.1.1. Downloading and Generating the High Performance Reference Design 5.1.2. Setting up CvP Parameters for CvP Initialization Mode 5.1.3. Compiling the Design for the CvP Initialization Mode 5.1.4. Splitting the SOF File for the CvP Initialization Design Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow x
5.2.1. Downloading and Generating the High Performance Reference Design 5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.2.4. Setting up CvP Parameters for CvP Initialization Mode 5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow 5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode x
5.3.1. Downloading and Generating the High Performance Reference Design 5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.3.4. Setting up CvP Parameters for CvP Update Mode 5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.3.6. Compiling the Design for the CvP Update Mode 5.3.7. Splitting the SOF File for the CvP Update Design Mode 5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
5.4. Bringing Up the Hardware x
5.4.1. Installing Jungo WinDriver in Windows Systems 5.4.2. Installing Jungo WinDriver in Linux Systems 5.4.3. Installing Open Source CvP Driver in Linux System 5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit 5.4.5. Programming CvP Images and Validating the Link
5.6. Known Issues and Solutions x
5.6.1. Using MSI-X in CvP Initialization Mode
6. CvP Driver and Registers x
6.1. CvP Driver Support 6.2. CvP Driver Flow 6.3. VSEC Registers for CvP
6.3. VSEC Registers for CvP x
6.3.1. Altera-defined Vendor Specific Capability Header Register 6.3.2. Altera-defined Vendor Specific Header Register 6.3.3. Altera Marker Register 6.3.4. CvP Status Register 6.3.5. CvP Mode Control Register 6.3.6. CvP Data Registers 6.3.7. CvP Programming Control Register 6.3.8. Uncorrectable Internal Error Status Register 6.3.9. Uncorrectable Internal Error Mask Register 6.3.10. Correctable Internal Error Status Register 6.3.11. Correctable Internal Error Mask Register
1. Overview
2. FPGA Configuration using CvP
3. CvP Topologies
4. Design Considerations
5. CvP Example Designs
6. CvP Driver and Registers
7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow

This section provides the instructions to create CvP revisions for the reconfigurable core logic region that can be updated. The remainder of the design is treated as a static core region.

Follow these steps to create the base version of the core logic:

  1. On the Assignments menu, select Settings and then select Files.
  2. In the File name box, Browse and select user_led.v, then click Add.
  3. Click OK.
  4. Run Analysis & Synthesis so that the Quartus Prime software parses the design to create a design hierarchy that includes the user_led instance.
  5. To set user_led as a design partition, right click user_led:user_led in the design hierarchy and select Design Partition. A small red box appears next to user_led :user:led indicating that it is a separate partition. (If you perform the same steps again, you remove the separate design partition from user_led:user_led.) The following image illustrates this step.
    Figure 43. Setting a Design Partition
  6. Click the Design Partitions Window at the bottom of the menu cascade shown in the figure above. The Design Partitions Window appears.
  7. To add the Allow Multiple Personas column to the Design Partitions Window , right click on the top bar of Design Partition Window next to the Color heading and select Allow Multiple Personas from the list as shown in the following figure.
    Figure 44. Allowing Multiple Personas
  8. Click the core instance user_led:user_led and set Allow Multiple Personas to On .
  9. Click in the Netlist Type column and set the user_led:user_led Netlist Type to Source File.
  10. Follow these steps to create a CvP revision for the modified project.
    1. Under the Revisions tab, right click on the Revision top and select Create CvP Revision. The Create CvP Revision dialog box appears.
    2. For the Revision Name type cvp_app and click OK to create a CvP revision as illustrated in the following figure.
      Figure 45. Specifying Revision Name
    3. Save the Quartus Prime project.
  11. Change the CvP revision in the Quartus Prime software design revision list as shown in the following figure.
    Figure 46. Changing the CvP Revision
  12. To remove user_led.v from the cvp_app revision, on the Assignments menu, select Settings , then select Files.
    This is the original user_led.v file that turns on the LED when the LTSSM enters the Polling.Compliance state.
  13. In the Files list, click user_led.v, then click Remove.
  14. To add cvp_app_src/user_led.v for the cvp_app revision, in the File name box, click Browse and browse to cvp_app_src/user_led.v, then click Add.
    This is the modified user_led.v file that turns on the LED when the bit[23] of a counter is one.
  15. In the File name box, click Browse and browse to cvp_app_src/user_led.v, then click Add.
  16. Click OK.
  17. In the Partition Name window, select user_led:user_led and change the Netlist Type to Source File and turn On Allow Multiple Personas.
  18. Change back to the top revision in the Quartus Prime software design revision list.
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