Visible to Intel only — GUID: nik1412546849319
Ixiasoft
Visible to Intel only — GUID: nik1412546849319
Ixiasoft
5. CvP Example Designs
The CvP process involves the interactions between the PCI Express host, the FPGA Control Block, the Stratix V Hard IP for PCI Express IP Core, and the CRAM in FPGA as indicated in the following figure. The Control Block and FPGA CRAM are hidden. You cannot access them. Consequently, you cannot simulate the CvP functionality.
Name | Description | |
---|---|---|
altpcied_sv.sdc |
Synopsys Design Constraints (.sdc) for the Hard IP for PCI Express IP Core. |
|
top_hw.sdc |
Top-level timing constraint file .sdc for the complete design. |
|
top_hw.v |
Top-level wrapper for the PCI Express High Performance Reference Design. |
|
top.cof |
CvP conversion file for CvP initialization mode. This file specifies the input and output files that Quartus Prime software requires to split the original .sof or .pof file into periphery and core images. |
|
pcie_lib |
Design files that are used by synthesis tools. |