Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5. CvP Example Designs

The example designs in this chapter illustrate the steps required for CvP initialization mode, CvP initialization with subsequent changes to the core logic, and CvP update mode. All of them start with the PCI Express High Performance Reference Design that you can download from the Altera website. The example designs also show how to use the CvP revision design flow to prepare the design for reconfigurable core logic.

The CvP process involves the interactions between the PCI Express host, the FPGA Control Block, the Stratix V Hard IP for PCI Express IP Core, and the CRAM in FPGA as indicated in the following figure. The Control Block and FPGA CRAM are hidden. You cannot access them. Consequently, you cannot simulate the CvP functionality.

Figure 11. Key Components in a CvP Design
Table 7.   Key Files for the CvP Qsys Example Design
Name Description

altpcied_sv.sdc

Synopsys Design Constraints (.sdc) for the Hard IP for PCI Express IP Core.

top_hw.sdc

Top-level timing constraint file .sdc for the complete design.

top_hw.v

Top-level wrapper for the PCI Express High Performance Reference Design.

top.cof

CvP conversion file for CvP initialization mode. This file specifies the input and output files that Quartus Prime software requires to split the original .sof or .pof file into periphery and core images.

pcie_lib

Design files that are used by synthesis tools.