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5.1. Understanding the Design Steps for CvP Initialization Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode
5.4. Bringing Up the Hardware
5.5. CvP Debugging Check List
5.6. Known Issues and Solutions
5.2.1. Downloading and Generating the High Performance Reference Design
5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region
5.2.4. Setting up CvP Parameters for CvP Initialization Mode
5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow
5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3.1. Downloading and Generating the High Performance Reference Design
5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core
5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region
5.3.4. Setting up CvP Parameters for CvP Update Mode
5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow
5.3.6. Compiling the Design for the CvP Update Mode
5.3.7. Splitting the SOF File for the CvP Update Design Mode
5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
6.3.1. Altera-defined Vendor Specific Capability Header Register
6.3.2. Altera-defined Vendor Specific Header Register
6.3.3. Altera Marker Register
6.3.4. CvP Status Register
6.3.5. CvP Mode Control Register
6.3.6. CvP Data Registers
6.3.7. CvP Programming Control Register
6.3.8. Uncorrectable Internal Error Status Register
6.3.9. Uncorrectable Internal Error Mask Register
6.3.10. Correctable Internal Error Status Register
6.3.11. Correctable Internal Error Mask Register
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1.6. Additional Information about PCI Express
The following links provide information about the PCI Express specifications and Altera's offerings for PCI Express.
Altera’s PCI Express IP cores and devices are complaint with the following PCI-SIG® specifications:
- PCI Express Base Specification, Rev 1.1 (2.5 GT/s)
- PCI Express Base Specification, Rev 2.0 (2.5 GT/s and 5.0 GT/s)
- PCI Express Specification, Rev 3.0 (2.5 GT/s, 5.0 GT/s, and 8.0 GT/s)
Related Information:
- Avalon-ST
- Avalon-MM
- Avalon-MM with DMA
- Single Root I/O Virtualization