Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow

To compile your project, click Compile All. Using Compile All guarantees that the Quartus Prime software compiles the top revision and cvp_app revision in the correct order.

Figure 33. Compile Both Base and cvp_app Revisions Using the Compile All Option in Quartus 13.0

You might need to go through a few iterations of compiling your designs to separate all of the periphery components from the core logic. As a result, the final design might not maintain the functional relationships between logic blocks that you originally planned. Adding extra comments in your design will help you to trace the HDL.

You must compile your project to update the reconfigured core image if any of the following conditions are true:

  • The CvP revision has never been compiled.
  • You have changed the periphery logic.
  • You have changed the wrapper file for any of the core revisions.
  • You have migrated to a new version of the Quartus Prime software.
  • You have changed any project settings in the Quartus Prime Settings File (*. qsf).