Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

4.1. Preparing the Design for CvP Revision Design Flow

The CvP revision design flow requires separate bitstreams for design elements implemented in the I/O ring (periphery) and FPGA core fabric. To use an I/O bitstream with multiple FPGA core fabric bitstreams, separate periphery elements from the reconfigurable core logic.

  • The I/O ring, or periphery partition controlled by I/O periphery register bits:
    • I/O registers
    • General-purpose I/Os (GPIOs)
    • Transceivers
    • Phase-locked loops (PLLs)
    • Hard IP for PCI Express
    • Hardened memory PHY
    • Global clocks (GCLK)
    • Regional clocks (RCLK)
  • The core partition: Core logic to program the FPGA fabric. The core logic contains both the static core region and the reconfigurable core region.
    • Reconfigurable region - This region can be programmed in user mode while the PCIe link is up and fully enumerated. It must contain only resources that are controlled by CRAM such as LABs, embedded RAM blocks, and DSP blocks in the FPGA core image. It cannot contain any periphery components such as GPIOs, transceivers, PLL, I/O blocks, the Hard IP for PCI Express IP Core, or other components included in the periphery image.
    • Static region - This region cannot be modified.
    You may create one or more partitions for the core fabric; however, only one partition can include the logic that you plan to reconfigure.

You must ensure the reconfigurable core logic does not contain any periphery components. Failure to make these connections results in the following Quartus Prime compilation error:

Error (142040): Detected illegal nodes in reconfigurable partitions. Only core logic is reconfigurable in this version of the Quartus Prime software.

Figure 7. Recommended Design HierarchyThe following figure shows the recommended design hierarchy for a design including the Hard IP PCI Express IP Core, an interface to DDR3 SDRAM, and core logic.


This design hierarchy represents the actual partition after the Quartus Prime compilation. You must ensure that the reconfigurable core logic does not contain any periphery elements. Separation of the core and peripheral logic is an iterative process and may take several Quartus Prime compilations to find all peripheral logic that needs to be isolated from reconfigurable core logic.