Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement

Estimating PCIe Wake-Up Time Requirement Equation


Conventions used for the equation:

  • Full configuration file size in bits—refer to uncompressed .rbf sizes.
  • Number of data lines—refer to the width of data bus. For example, the width of data bus for FPP x16 is 16.
  • DCLK frequency—refer to fMAX for the DCLK frequency.
  • Power ramp up—must be within 10 ms.
  • POR delay—use fast POR, maximum time is 12 ms.

You can use the equation above to estimate whether your device meets the PCIe wake-up time requirement. The following figure shows an example calculation for the PCIe wake-up time requirement on an Arria V GX A5 device.

Example Calculation of PCIe Wake-Up Time Requirement


The estimation for Arria V GX A5 device is 72 ms, which meets the PCIe wake-up time requirement of 120 ms.