Visible to Intel only — GUID: nik1412546837043
Ixiasoft
Visible to Intel only — GUID: nik1412546837043
Ixiasoft
1.3. CvP Modes
The CvP configuration scheme supports the following modes:
- CvP initialization mode
- CvP update mode
CvP Initialization Mode
This mode configures the core of the FPGA through the PCIe link upon system power up. Initialization refers to the initial fabric configuration image loaded in the FPGA fabric after power up.
Benefits of using CvP initialization mode include:
- Satisfying the PCIe wake-up time requirement
- Saving cost by storing the core image in the host memory
- Preventing unauthorized access to the core image
CvP Update Mode
This mode assumes that you have configured the FPGA with the full configuration image (both periphery and core) from a local configuration device after the initial system power up. The PCIe link is used for subsequent core image updates (only core, the periphery must remain unchanged during CvP update).
Choose this mode if you want to update the core image for any of the following reasons:
- To change core algorithms
- To perform standard updates as part of a release process
- To customize core processing for different components that are part of a complex system
Device | CvP Modes Supported | ||
---|---|---|---|
PCIe Gen 1 | PCIe Gen 2 | PCIe Gen 3 | |
Arria 10 1 | CvP Initialization | CvP Initialization | CvP Initialization |
Stratix® V | CvP Initialization CvP Update |
CvP Initialization CvP Update |
No support |
Arria® V GZ | CvP Initialization CvP Update |
CvP Initialization CvP Update |
No support |
Arria® V | CvP Initialization CvP Update |
CvP Initialization | No support |
Cyclone® V | CvP Initialization CvP Update |
CvP Initialization | No support |