Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow

The CvP initialization mode with the revision design flow allows you to create a reconfigurable core image that work with the single periphery image. The core image is stored in host memory. You download the core image to the FPGA using the PCI Express link. By using the Revision Design Flow, you can change the core image after the initial download to run alternate versions of the core logic.

You specify this mode in the Quartus Prime software by selecting the CvP Settings Core initialization and update. When the FPGA is fully programmed, the FPGA enters user mode. In user mode, you can reprogram the original static core image. The following are typical reasons to choose CvP initialization mode:

  • To satisfy the PCIe initial power up requirement for plug-in cards if FPGA programming time exceeds this limit
  • To save cost by storing the core image in external host memory
  • To prevent unauthorized access to the core image by using encryption
  • To change the core logic the following reasons:
    • To customize the core logic for different tasks
    • To provide periodic revisions for routine maintenance of the core logic

If you plan to create multiple versions of the core logic for the same periphery I/O, the new core images might not work with the previous periphery image. You can use the CvP Revision Design Flow to create reconfigurable images that connect to the same periphery image.

Figure 21. Design Flow for the CvP Initialization Mode with the Revision Design Flow
Note: When you select CvP initialization mode, you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP.