Visible to Intel only — GUID: nik1412546910880
Ixiasoft
Visible to Intel only — GUID: nik1412546910880
Ixiasoft
5.1. Understanding the Design Steps for CvP Initialization Mode
CvP initialization mode divides the design into periphery and core images. The periphery image can be stored in a local flash device on the PCB and the user can program the periphery via Active Serial (AS) mode. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.
You must specify CvP initialization mode in the Quartus Prime software by selecting the CvP Settings Core initialization and update. You might choose CvP initialization mode for any of the following reasons:
- To save cost by storing the core image in external host memory.
- To prevent unauthorized access to the core image by storing it on the host.