Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.1. Understanding the Design Steps for CvP Initialization Mode

CvP initialization mode divides the design into periphery and core images. The periphery image can be stored in a local flash device on the PCB and the user can program the periphery via Active Serial (AS) mode. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.

Note: If you plan to create multiple versions of the core logic for the same periphery I/O, the new core images must work with the previous periphery image. Refer to Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow for information about how to create reconfigurable images that connect to the same periphery image.

You must specify CvP initialization mode in the Quartus Prime software by selecting the CvP Settings Core initialization and update. You might choose CvP initialization mode for any of the following reasons:

  • To save cost by storing the core image in external host memory.
  • To prevent unauthorized access to the core image by storing it on the host.
Figure 12. Design Flow for CvP Initialization Mode
Note: When you select CvP initialization mode, you must use the CMU PLL and the hard reset controller for the PCI Express Hard IP.