Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

2.1. CvP Configuration Images

In CvP, you partition your design into two images: core image and periphery image.

You use the Quartus Prime software to generate the images:
  • Periphery image (*.periph.jic)—contains general purpose I/Os (GPIOs), I/O registers, the GCLK, QCLK, and RCLK clock networks, PLLs, transceivers, hardened memory PHY and logic that is implemented in hard IP such as the JTAG interface, PR block, CRC block, Oscillator block, Impedance control block, Chip ID, ASMI block, Remote update block, Temperature sensor, and Hard IP for PCI Express IP Core. These components are included in the periphery image because they are controlled by I/O periphery register bits. The entire periphery image is static and cannot be reconfigured.
  • Core image (*.core.rbf)—contains logic that is programmed by configuration RAM (CRAM). This image includes LABs, DSP, and embedded memory. The core image consists of a single reconfigurable region or both static and reconfigurable regions.
    • Reconfigurable region - This region can be programmed in user mode while the PCIe link is up and fully enumerated. It must contain only resources that are controlled by CRAM such as LABs, embedded RAM blocks, and DSP blocks in the FPGA core image. It cannot contain any periphery components such as GPIOs, transceivers, PLLs, I/O blocks, the Hard IP for PCI Express IP Core, or other components included in the periphery image.
    • Static region - This region cannot be modified.