Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

2.2.2. CvP Update Mode

In this mode, the FPGA device is initialized after initial system power up by loading the full configuration image from the external local configuration device to the FPGA.

After the full FPGA configuration image is complete, the CONF_DONE signal goes high.

After the FPGA is fully configured, the FPGA enters initialization and user mode. If the INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is completed and the FPGA enters user mode.

In user mode, the PCIe links are available for normal PCIe applications. You can use the PCIe link to perform an FPGA core image update. To perform the FPGA core image update, you can create one or more FPGA core images in the Quartus Prime software that have identical connections to the periphery image.

Note: You cannot combine the features of CvP update mode and CvP initialization mode in a single design. For example, you cannot create a CvP update image for your Quartus Prime project and then specify a CvP initialization periphery image in your configuration scheme.