Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.3.7. Splitting the SOF File for the CvP Update Design Mode

Follow these steps to split your to create file into periphery and core images for CvP update mode. You use the core image, top.core.rbf, to perform CvP updates.

  1. On the File menu, select Convert Programming File.
  2. Under Output programming file specify the options in the following table. These options are illustrated in the figure below.
    Table 21.   Output Programming File

    Parameter

    Value

    Programming file type

    Programmer Object File (.pof)

    Configuration device

    CFI_128Mb

    Mode

    1-bit Passive Serial

    File name

    Click browse and specify pcie_quartus_files/top.pof.

    Create Memory Map File

    Turn this option on.

    Create CvP files

    Turn this option on. This box is greyed out until you specify the SOF Data file under Input files to convert.

  3. Under Input files to convert specify the options in the following table:
    Table 22.   Input files to convert

    Parameter

    Value

    Click SOF Data

    Click Add File and navigate to ./pcie_quartus_files/top.sof. If you specified a compressed or encrypted bitstream in the Device and Pin Options dialog box, you must specify the same options in the Conversion Programming File window. To enable these settings, click top.sof, then click Properties and check the appropriate boxes.

  4. Turn on the Create CvP files (Generate top.periph.jic and top.core.rbf) parameter in the Output Programming Files section.
  5. Click Generate to create top.periph.pof, and top.core.rbf. The periphery file, top.periph.pof is generated, but it is not used.
Figure 47. Base Revision of CvP Update Mode: Convert Programming File Settings
Note: The Configuration scheme and Configuration device in Device and Pin Options must match with Configuration Device and Mode in Convert Programming File respectively.