Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode

For CvP initialization mode, the Hard IP for PCI Express IP core is guaranteed to meet the 120 ms requirement because the periphery image configuration time is significantly less than the full FPGA configuration time. Therefore, you can choose any of the conventional configuration schemes for the periphery image configuration.

To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP initialization mode, the PCIe link supports the FPGA core image configuration and PCIe applications in user mode.

Note: For Gen 2 capable Endpoints, after loading the core .sof, Altera recommends that you verify that the link has been trained to the expected Gen 2 rate. If the link is not operating at Gen 2, host software can trigger the Endpoint to retrain.
Figure 9. PCIe Timing Sequence in CvP Initialization Mode


Table 4.  Power-Up Sequence Timing in CvP Initialization Mode
Timing Sequence Timing Range (ms) Description
a 10 Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range.
b 4–12 FPGA POR delay time.
c 100 Minimum PERST# signal active time from the host.
d 20 Minimum PERST# signal inactive time from the host before the PCIe link enters training state.
e 120 Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode.
f 100 Maximum time PCIe device must enter L0 after PERST# is deasserted.