Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit

The MSEL switch labeled SW4 on the back of the Stratix V GX FPGA Development Kit PCB specifies the flash type. The correct setting for an active serial x4 flash is 5’b10010 as shown in the following figure. The factory default value is 5'b01000.

Figure 49. Switch 4 (SW4) Configuration for MSEL[4:0] =5’b10010 on the back view of Stratix V Device Kit

In this figure, the switch head is outlined by a green rectangle. The up position signifies logic zero and the down position signifies logic one. The MSB of the switch, SW4[6], is on the far right. This bit is unused and must be set to zero (SW4[6]=up). The MSB bit of MSEL[4] is position 5, the second bit from the right. To set the unused bit to 0 and MSEL[4:0] = 5’b10010, the SW4[6:1] sequence is up(0), down(1), up(0), up(0), down(1), up(0), reading from right to left.