Visible to Intel only — GUID: nik1412546903027
Ixiasoft
Visible to Intel only — GUID: nik1412546903027
Ixiasoft
4.2.2.2.1. Recommended Configuration Schemes
For CvP initialization mode, you can configure the FPGA with the periphery image using the AS, PS, or FPP configuration scheme.
For CvP update mode, you can configure the FPGA fully using one of the configuration schemes listed in the table below. The table lists the configuration schemes based on the fastest DCLK frequency with data compression and encryption features disabled in the CvP update mode. These features require different data to clock ratios, which prolongs total configuration time. Consequently, total configuration time does not meet the 200-ms PCIe wake-up timing specification.
Variant | Member Code | Configuration Scheme |
---|---|---|
Arria V GX | A1 | FPP x8 FPP x16 |
A3 | ||
A5 | FPP x16 |
|
A7 | ||
B1 | ||
B3 | ||
B5 | ||
B7 | ||
Arria V GT | C3 | FPP x8 FPP x16 |
C7 | FPP x16 |
|
D3 | ||
D7 | ||
Arria V GZ | E1 | FPP x16 FPP x32 |
E3 | ||
E5 | FPP x32 |
|
E7 | ||
Arria V SX | B3 | FPP x16 |
B5 | ||
Arria V ST | D3 | FPP x16 |
D5 | ||
Cyclone V GX | C3 | AS x4 FPP x8 FPP x16 |
C4 | FPP x8 FPP x16 |
|
C5 | ||
C7 | ||
C9 | FPP x16 |
|
Cyclone V GT | D5 | FPP x8 FPP x16 |
D7 | ||
D9 | FPP x16 |
|
Cyclone V SX | C2 | TBD |
C4 | ||
C5 | FPP x8 FPP x16 |
|
C6 | ||
Cyclone V ST | D5 | FPP x8 FPP x16 |
D6 | ||
Stratix V GX | A3 | FPP x16 FPP x32 |
A4 | ||
A5 | FPP x32 |
|
A7 | ||
A9 | — | |
AB | ||
B5 | FPP x32 |
|
B6 | ||
B9 | — | |
BB | ||
Stratix V GT | C5 | FPP x32 |
C7 | ||
Stratix V GS | D3 | FPP x8 FPP x16 FPP x32 |
D4 | FPP x16 FPP x32 |
|
D5 | ||
D6 | FPP x32 |
|
D8 |