Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode

For CvP update mode, you initialize the FPGA by configuring it using one of the conventional configuration schemes upon device power-up. An open system requires that the FPGA initialization complete within 120 ms. To ensure that this requirement is met, choose the right conventional configuration scheme for your system.

To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. PERST# is one of the auxiliary signals specified in the PCIe electromechanical specification. The PERST# signal is sent from the PCIe host to the FPGA. The PERST# signal indicates whether the power supplies of the FPGA are within their specified voltage tolerances and are stable. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. The PERST# signal also initializes the FPGA state machines and other logic after power supplies are stabilized. The PCIe link supports PCIe applications in user mode for CvP update mode, therefore, you can use the PCIe link for core image update.

Note: For Gen 2 capable Endpoints, after loading the core .sof, Altera recommends to verify that the link has been trained to the expected Gen 2 rate. If the link is not operating at Gen 2, software can trigger the Endpoint to retrain.
Figure 10. PCIe Timing Sequence in CvP Update Mode


Table 5.  Power-Up Sequence Timing in CvP Update Mode
Timing Sequence Timing Range (ms) Description
a 10 Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range.
b 4–12 FPGA POR delay time.
c 100 Minimum PERST# signal active time from the host.
d 20 Minimum PERST# signal inactive time from the host before the PCIe link enters training state.
e 120 Maximum time from the FPGA power up to the end of the full FPGA configuration in CvP update mode.
f 100 Maximum time PCIe device must enter L0 after PERST# is deasserted.