Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

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ID 683889
Date 9/04/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FPGA Configuration using CvP 3. CvP Topologies 4. Design Considerations 5. CvP Example Designs 6. CvP Driver and Registers 7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes 1.4. CvP Revision Design Flow 1.5. CvP Topologies 1.6. Additional Information about PCI Express
2. FPGA Configuration using CvP x
2.1. CvP Configuration Images 2.2. CvP Modes 2.3. Alternative to CvP Initialization: Autonomous HIP Mode 2.4. CvP Compression and Encryption Features 2.5. Core Image Update 2.6. CvP Pins
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
2.4. CvP Compression and Encryption Features x
2.4.1. Data Compression 2.4.2. Data Encryption
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints 3.3. Mixed Chain
3.3. Mixed Chain x
3.3.1. Configuring Slave FPGAs with Different Configuration Files 3.3.2. Configuring Slave FPGAs with a Single Configuration File
4. Design Considerations x
4.1. Preparing the Design for CvP Revision Design Flow 4.2. Designing CvP for an Open System 4.3. Designing CvP for a Closed System 4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller
4.2. Designing CvP for an Open System x
4.2.1. FPGA Power Supplies Ramp Time Requirement 4.2.2. PCIe Wake-Up Time Requirement
4.2.2. PCIe Wake-Up Time Requirement x
4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode 4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode
4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode x
4.2.2.2.1. Recommended Configuration Schemes 4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement
5. CvP Example Designs x
5.1. Understanding the Design Steps for CvP Initialization Mode 5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5.3. Understanding the Design Steps for CvP Update Mode 5.4. Bringing Up the Hardware 5.5. CvP Debugging Check List 5.6. Known Issues and Solutions
5.1. Understanding the Design Steps for CvP Initialization Mode x
5.1.1. Downloading and Generating the High Performance Reference Design 5.1.2. Setting up CvP Parameters for CvP Initialization Mode 5.1.3. Compiling the Design for the CvP Initialization Mode 5.1.4. Splitting the SOF File for the CvP Initialization Design Mode
5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow x
5.2.1. Downloading and Generating the High Performance Reference Design 5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.2.4. Setting up CvP Parameters for CvP Initialization Mode 5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow 5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow
5.3. Understanding the Design Steps for CvP Update Mode x
5.3.1. Downloading and Generating the High Performance Reference Design 5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.3.4. Setting up CvP Parameters for CvP Update Mode 5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.3.6. Compiling the Design for the CvP Update Mode 5.3.7. Splitting the SOF File for the CvP Update Design Mode 5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow
5.4. Bringing Up the Hardware x
5.4.1. Installing Jungo WinDriver in Windows Systems 5.4.2. Installing Jungo WinDriver in Linux Systems 5.4.3. Installing Open Source CvP Driver in Linux System 5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit 5.4.5. Programming CvP Images and Validating the Link
5.6. Known Issues and Solutions x
5.6.1. Using MSI-X in CvP Initialization Mode
6. CvP Driver and Registers x
6.1. CvP Driver Support 6.2. CvP Driver Flow 6.3. VSEC Registers for CvP
6.3. VSEC Registers for CvP x
6.3.1. Altera-defined Vendor Specific Capability Header Register 6.3.2. Altera-defined Vendor Specific Header Register 6.3.3. Altera Marker Register 6.3.4. CvP Status Register 6.3.5. CvP Mode Control Register 6.3.6. CvP Data Registers 6.3.7. CvP Programming Control Register 6.3.8. Uncorrectable Internal Error Status Register 6.3.9. Uncorrectable Internal Error Mask Register 6.3.10. Correctable Internal Error Status Register 6.3.11. Correctable Internal Error Mask Register
1. Overview
2. FPGA Configuration using CvP
3. CvP Topologies
4. Design Considerations
5. CvP Example Designs
6. CvP Driver and Registers
7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

2.6. CvP Pins

The following table lists the CvP pin descriptions and connection guidelines.
Table 3.  CvP pin descriptions and connection guidelines
Pin Name Pin Type Pin Description Pin Connection
CvP_CONFDONE Output

The CvP_CONFDONE pin is driven low during configuration. When configuration via PCIe is complete, this signal is released and either actively driven high, or pulled high by an external pull-up resistor.

During FPGA configuration in CvP initialization mode, you must observe this pin after the CONF_DONE pin goes high to determine if the FPGA is successfully configured.

If you are not using the CvP modes, you can use this pin as a user I/O pin.

If this pin is set as dedicated output, the VCCPGM power supply must meet the input voltage specification of the receiving side.

If this pin is set as an open-drain output, connect the pin to an external 10-kΩ pull-up resistor to the VCCPGM power supply or a different pull-up voltage that meets the input voltage specification of the receiving side. This gives an advantage on the voltage leveling.

INIT_DONE Output When you enable this pin, a transition from low to high at the pin indicates the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

This is a dual-purpose pin and can be used as an I/O pin when not enabled as the INIT_DONE pin.

When you use the optionally open-drain output dedicated INIT_DONE pin, connect this pin to an external 10-kΩ pull-up resistor to VCCPGM.

When you use this pin in an AS or PS multi-device configuration mode, ensure you enable the INIT_DONE pin in the Quartus Prime designs. When you do not use the dedicated INIT_DONE optionally open-drain output, and when this pin is not used as an I/O pin, connect this pin as defined in the Quartus Prime software.

CONF_DONE Bidirectional Dedicated configuration done pin.

As a status output, the CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, CONF_DONE is released.

As a status input, the CONF_DONE pin goes high after all data is received. Then the device initializes and enters user mode. This pin is not available as a user I/O pin.

Connect an external 10-kΩ pull-up resistors to VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host.

When you use passive configuration schemes, the configuration controller monitors this pin.

nPERST[L,R][0:1] Input

This pin is connected to the Hard IP for PCI Express IP Core as a dedicated fundamental reset pin for PCIe usage. If the signal is low, the transceivers and dedicated PCIe Hard IP block that you use for CvP operation are in the reset mode.

Connect the nPERST[L,R]0/nPERST[L,R]1 to the PERST# pin of the PCIe slot. This pin may be driven by 3.3V compatible I/O standards. Only one nPERST pin is used per instances of Hard IP for PCI Express.

In Arria V and Stratix V devices, these pins have the following locations:
  • nPERSTL0 = Bottom Left PCIe Hard IP & CvP
  • nPERSTL1 = Top Left PCIe Hard IP (When available)
  • nPERSTR0 = Bottom Right PCIe Hard IP (When available)
  • nPERSTR1 = Top Right PCIe Hard IP (When available)
In Cyclone V devices, these pins have the following locations:
  • nPERSTL0 = Top Left PCIe Hard IP
  • nPERSTL1 = Bottom Left PCIe Hard IP & CvP
Note: For maximum compatibility, always use the bottom left PCIe Hard IP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe link.
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