Visible to Intel only — GUID: nik1412546854701
Ixiasoft
Visible to Intel only — GUID: nik1412546854701
Ixiasoft
2.5. Core Image Update
After the FPGA enters user mode, the PCIe host can trigger an FPGA core image update through the PCIe link. Both CvP initialization mode and CvP update mode support core images updates.
You must choose the same bitstream settings for all core images. For example, if you have selected either encryption, compression, or both encryption and compression features for the first core image, you must ensure you turned on the same features for the other core images that you will use for core image update using CvP.
You can use CvP revision design flow to create multiple reconfigurable core images that connect to the same periphery image.
When you initiate a core image update, the CvP_CONFDONE pin is pulled low, indicating a core image update has started. The FPGA fabric is reinitialized and reconfigured with the new core image. During the core image update through a PCIe link, the nCONFIG and nSTATUS pins of the FPGA remain at logic high. When the core image update completes, the CvP_CONFDONE pin is released high, indicating the FPGA has entered user mode.