Intel® Arria® 10 SoC UEFI Boot Loader User Guide

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ID 683536
Date 12/15/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC UEFI Boot Loader User Guide
1. Intel® Arria® 10 SoC UEFI Boot Loader User Guide x
1.1. Acronyms and Definitions 1.2. Recommended System Requirements 1.3. Installation Folders 1.4. Boot Flow Overview 1.5. Getting Started 1.6. Enabling the UEFI DXE Phase and the UEFI Shell 1.7. Using the Network Feature Under the UEFI Shell 1.8. Creating your First UEFI Application 1.9. Using Arm* DS-5* Intel® SoC FPGA Edition (For Windows* Only) 1.10. Pit Stop Utility Guide 1.11. Porting HWLIBs to UEFI Guidelines 1.12. Tera Term Installation 1.13. Minicom Installation 1.14. Win32DiskImager Tool Installation 1.15. TFTPd64 By Ph.Jounin Installation 1.16. Revision History of Intel® Arria® 10 SoC UEFI Boot Loader User Guide
1.2. Recommended System Requirements x
1.2.1. Minimum Hardware Requirements 1.2.2. Minimum Software Requirements
1.5. Getting Started x
1.5.1. Compiling the Hardware Design 1.5.2. Generating the Boot Loader and Device Tree for UEFI Boot Loader 1.5.3. Building the UEFI Boot Loader 1.5.4. Creating an SD Card Image 1.5.5. Creating a QSPI Image 1.5.6. Booting the Board with SD/MMC 1.5.7. Booting the Board with QSPI 1.5.8. Early I/O Release 1.5.9. Booting Linux* Using the UEFI Boot Loader 1.5.10. Debugging an Example Project 1.5.11. UEFI Boot Loader Customization 1.5.12. Enabling Checksum for the FPGA Image 1.5.13. NAND Bad Block Management
1.5.1. Compiling the Hardware Design x
1.5.1.1. Open a Intel® Quartus® Prime Project 1.5.1.2. Generate the System in Platform Designer 1.5.1.3. Compile the Design in Intel® Quartus® Prime 1.5.1.4. Converting the Programming File
1.5.1.4. Converting the Programming File x
1.5.1.4.1. Converting the SOF File into Two Split RBF Files 1.5.1.4.2. Converting the SOF File into a Single RBF File 1.5.1.4.3. Single RBF Conversion Using the GUI Converter 1.5.1.4.4. Single RBF Conversion Using the Intel® Quartus® Prime Pro Edition Programmer Command Line Tools
1.5.2. Generating the Boot Loader and Device Tree for UEFI Boot Loader x
1.5.2.1. Generating the Boot Loader DTS File for 16.0 Release and Below 1.5.2.2. Generating a Boot Loader DTB File for the 16.0 Release and Below 1.5.2.3. Generating the Boot Loader DTS File for the 16.1 Release 1.5.2.4. Generating a Boot Loader DTB File for the 16.1 Release
1.5.2.1. Generating the Boot Loader DTS File for 16.0 Release and Below x
1.5.2.1.1. Windows* Environment 1.5.2.1.2. Linux* Environment
1.5.2.3. Generating the Boot Loader DTS File for the 16.1 Release x
1.5.2.3.1. Windows* Environment 1.5.2.3.2. Linux* Environment
1.5.3. Building the UEFI Boot Loader x
1.5.3.1. Prerequisites 1.5.3.2. Supported Compiler Toolchain 1.5.3.3. Obtaining the UEFI Source Code 1.5.3.4. Preparing the Handoff DTB 1.5.3.5. Compiling the UEFI 1.5.3.6. Generated Files from UEFI Compile
1.5.3.4. Preparing the Handoff DTB x
1.5.3.4.1. Updating the Device Tree Blob
1.5.3.5. Compiling the UEFI x
1.5.3.5.1. Compiling the UEFI in a Windows Environment 1.5.3.5.2. Compiling the UEFI in the Linux Environment 1.5.3.5.3. Compiling the UEFI with the ARMCC Compiler
1.5.4. Creating an SD Card Image x
1.5.4.1. Creating an SD Card Image on Linux 1.5.4.2. Creating an SD Card Image on Windows* 1.5.4.3. Compile the Bare Metal Application Source Code 1.5.4.4. Updating Individual Elements on the SD Card
1.5.4.4. Updating Individual Elements on the SD Card x
1.5.4.4.1. Programming the Bare Metal Image 1.5.4.4.2. Programming the Integrity Real-Time Operating System Image 1.5.4.4.3. Programming the VxWorks* Real-Time Operating System Image
1.5.5. Creating a QSPI Image x
1.5.5.1. Updating the Golden Hardware Reference Design to Boot from QSPI 1.5.5.2. Compiling the Hardware and Software for QSPI 1.5.5.3. Compiling the UEFI Source Code with the Updated QSPI Device Tree Blob 1.5.5.4. QSPI Layout 1.5.5.5. Updating Individual Elements into the QSPI
1.5.5.5. Updating Individual Elements into the QSPI x
1.5.5.5.1. Programming the Bare Metal Image 1.5.5.5.2. Programming the Integrity Real-Time Operating System Image 1.5.5.5.3. Programming the VxWorks* Real-Time Operating System Image
1.5.6. Booting the Board with SD/MMC x
1.5.6.1. Configuring the Board 1.5.6.2. Configuring the Serial Connection 1.5.6.3. Booting a Bare Metal Application from SD/MMC 1.5.6.4. Booting Integrity Real-Time Operating System from SD/MMC 1.5.6.5. Booting from VxWorks* Real-Time Operating System from SD/MMC
1.5.7. Booting the Board with QSPI x
1.5.7.1. Configuring the Board 1.5.7.2. Configuring the Serial Connection 1.5.7.3. Booting a Bare Metal Application from QSPI 1.5.7.4. Booting Integrity Real-Time Operating System from QSPI 1.5.7.5. Booting from VxWorks* Real-Time Operating System from QSPI
1.5.8. Early I/O Release x
1.5.8.1. Boot Flow 1.5.8.2. Enabling Early I/O Release 1.5.8.3. Device Tree Support 1.5.8.4. Early I/O Release Output Messages
1.5.8.2. Enabling Early I/O Release x
1.5.8.2.1. Automatically Loaded Peripheral RBF and Core RBF 1.5.8.2.2. Automatically Loaded Peripheral RBF And Manually Loaded RBF Through Pit Stop 1.5.8.2.3. Automatically Loaded Combined RBF
1.5.9. Booting Linux* Using the UEFI Boot Loader x
1.5.9.1. Boot Linux* Support 1.5.9.2. Prerequisites 1.5.9.3. Booting Linux from the PEI Phase 1.5.9.4. Booting Linux from the DXE Phase
1.5.9.3. Booting Linux from the PEI Phase x
1.5.9.3.1. Booting Linux* from the PEI Phase Automatically 1.5.9.3.2. Booting Linux from the PEI Phase Using SD/MMC or QSPI Manually
1.5.9.4. Booting Linux from the DXE Phase x
1.5.9.4.1. Booting Linux from the DXE Phase Using SD/MMC 1.5.9.4.2. Booting Linux* from the DXE Phase Using SD/MMC Manually 1.5.9.4.3. Booting Linux* from the DXE Phase Using SD/MMC Automatically
1.5.10. Debugging an Example Project x
1.5.10.1. Configuring and Starting the Debugger in Eclipse 1.5.10.2. Setting a Breakpoint 1.5.10.3. Watching Variable Contents
1.5.11. UEFI Boot Loader Customization x
1.5.11.1. Changing the Platform Name 1.5.11.2. Turning Off the Debug Features for Production Release 1.5.11.3. Modifying the UART Port Number for Serial Terminal Messages 1.5.11.4. Adding Custom Board Initialization Code
1.5.12. Enabling Checksum for the FPGA Image x
1.5.12.1. Configuration in UEFI 1.5.12.2. Generate mkimage
1.5.13. NAND Bad Block Management x
1.5.13.1. Bad Block Marker 1.5.13.2. Bad Block Handling
1.7. Using the Network Feature Under the UEFI Shell x
1.7.1. Obtain the IP Address from the DHCP Server 1.7.2. Use a Static IP Address 1.7.3. Ping Test 1.7.4. TFTP Test
1.9. Using Arm* DS-5* Intel® SoC FPGA Edition (For Windows* Only) x
1.9.1. Importing the DS-5 Project 1.9.2. Building UEFI in Arm* DS-5* Intel® SoC FPGA Edition 1.9.3. Importing the Arm* DS-5* Intel® SoC FPGA Edition Debug Script
1.10. Pit Stop Utility Guide x
1.10.1. Enabling or Disabling the Pit Stop Utility 1.10.2. Pit Stop Utility Commands and Use
1.10.2. Pit Stop Utility Commands and Use x
1.10.2.1. Memory and Memory-Mapped I/O Commands 1.10.2.2. QSPI Flash Commands 1.10.2.3. NAND Flash Commands 1.10.2.4. SD/MMC Commands 1.10.2.5. FAT32 File System Commands 1.10.2.6. Others 1.10.2.7. Help
1.11. Porting HWLIBs to UEFI Guidelines x
1.11.1. Coding Standard 1.11.2. Data Types Conversion 1.11.3. Status Code Conversion 1.11.4. Header Conversion 1.11.5. Basic I/O Functions Conversion
1.11.1. Coding Standard x
1.11.1.1. General Rules 1.11.1.2. Naming Conventions 1.11.1.3. Type and Macro Names 1.11.1.4. Variables 1.11.1.5. Function 1.11.1.6. Comment
1.12. Tera Term Installation x
1.12.1. Making a Serial Connection
1.13. Minicom Installation x
1.13.1. Making a Serial Connection
1.14. Win32DiskImager Tool Installation x
1.14.1. Using Win32Disk Imager
1.15. TFTPd64 By Ph.Jounin Installation x
1.15.1. Checking Your Machine or Laptop IPv4 Address 1.15.2. Enabling the TFTP Server through the Windows* Firewall 1.15.3. Using the TFTP Server in Windows*
1. Intel® Arria® 10 SoC UEFI Boot Loader User Guide

1.5.1. Compiling the Hardware Design

Task Time: 30 Minutes

If you make any changes, you must re-compile the design that is packaged in the SoC FPGA EDS. Otherwise, you can directly work with the pre-compiled design. As an example, the following sections describe how to compile the hardware design packaged in the SoC FPGA EDS.


Section Content
Open a Intel Quartus Prime Project
Generate the System in Platform Designer
Compile the Design in Intel Quartus Prime
Converting the Programming File

Level Two Title