GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4. IP Architecture and Functional Description

This chapter describes the architecture details of the GTS AXI Streaming IP and details the various blocks and modes available in the IP that you can use.
The Agilex 5 FPGAs and SoCs provide two variants of the PCIe* Hard IP: PCIe* 4.0 x8 Hard IP for the performance-optimized D-Series FPGAs and PCIe 4.0 x4 Hard IP for the power-optimized E-Series FPGAs. The GTS AXI Streaming IP is built on the PCIe* Hard IP block. It consists of the following major sub-blocks:
  • PCIe* Hard IP (HIP) which consist of PMA, PCS, PIPE, PCIe* controller, and PLD interface.
  • Soft logic blocks in the FPGA fabric to serve as an adapter between User Logic and HIP to allow user to configure the IP and access to the features supported by HIP. Besides, it also implements functions such as VirtIO, and others.
Attention: pin_perst_n shall constitute a reference to the input port for PERST# function. Refer to Interface Reset Signals section for the port name.
Figure 5.  GTS AXI Streaming IP Block Diagram for E-Series FPGAs
Figure 6.  GTS AXI Streaming IP Block Diagram for D-Series FPGAs

The HIP implements Physical, Data Link and Transaction Layers of the PCIe* protocol. The HIP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for handling virtualization. The System PLL generates the clock to drive the PLD interface and the output clock to drive application logic.

In E-Series devices, x4 HIP is supported in every GTS bank. In D-Series devices, two GTS banks are combined to support x8 mode where the x8 controller and the system PLL in the upper bank are active. However, the x8 HIP can also be configured to support two independent x4 links.
Figure 7. Example of Agilex 5 D-Series x8 HIP Configured to Support x8 or x4 Mode(1)

There are reference clock pins and a System PLL in each transceiver bank, and reset pins in the HVIO banks to enable independent PCIe* links. Only one PCIe* link is allowed in each GTS bank, except x8 mode which occupies two banks. The valid PCIe* link placements are shown in the following figure. When a PCIe* link is configured as x1 or x2 mode, the remaining channels in the same bank can be configured as non- PCIe* channels and the System PLL for the non- PCIe* channels comes from another GTS bank.

Figure 8.  PCIe* Link and Lanes Placements
Note: For details of System PLL output clock network, refer to Implementing the GTS System PLL Clocks Intel® FPGA IP section in GTS Transceiver PHY User Guide