Visible to Intel only — GUID: wke1696474983040
Ixiasoft
Visible to Intel only — GUID: wke1696474983040
Ixiasoft
4. IP Architecture and Functional Description
- PCIe* Hard IP (HIP) which consist of PMA, PCS, PIPE, PCIe* controller, and PLD interface.
- Soft logic blocks in the FPGA fabric to serve as an adapter between User Logic and HIP to allow user to configure the IP and access to the features supported by HIP. Besides, it also implements functions such as VirtIO, and others.
The HIP implements Physical, Data Link and Transaction Layers of the PCIe* protocol. The HIP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SR-IOV functionality for handling virtualization. The System PLL generates the clock to drive the PLD interface and the output clock to drive application logic.
There are reference clock pins and a System PLL in each transceiver bank, and reset pins in the HVIO banks to enable independent PCIe* links. Only one PCIe* link is allowed in each GTS bank, except x8 mode which occupies two banks. The valid PCIe* link placements are shown in the following figure. When a PCIe* link is configured as x1 or x2 mode, the remaining channels in the same bank can be configured as non- PCIe* channels and the System PLL for the non- PCIe* channels comes from another GTS bank.
Section Content
Clocking
Resets
PCIe Hard IP
Hard IP Interface (IF) Adaptor
Interrupts
Transaction Ordering
TX Non-Posted Metering Requirement on Application
AXI4-Stream Interface
Tag Allocation
Precision Time Measurement (PTM)
Single Root I/O Virtualization (SR-IOV)
Transaction Layer Packet (TLP) Bypass Mode
Scalable IOV