Visible to Intel only — GUID: pcc1696958278327
Ixiasoft
Visible to Intel only — GUID: pcc1696958278327
Ixiasoft
7.14. Miscellaneous Signals
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
p<n>_ss_app_serr | Output | p<n>_axi_st_clk | Indicates System Error is detected. In TLP Bypass mode indicates physical, data link, and transaction layer error detected by the PCIe* Hard IP. |
p<n>_ss_app_dlup | Output | p<n>_axi_st_clk | When asserted, this signal indicates Data Link Layer is up. |
p<n>_ss_app_linkup | Output | p<n>_axi_st_clk | When asserted, this signal indicates the link is up. |
p<n>_ss_app_int_status | Output | p<n>_axi_st_clk | This signal drives legacy interrupts to the Application Layer. The source of the interrupt is logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.
Note: Applicable only in Root Port Mode.
|
p<n>_ss_app_surprise_down_err | Output | Async | Indicates that a surprise down event is occurring in the PCIe* Hard IP controller. Applicable for Downstream Port mode only. |
p<n>_ss_app_ltssmstate[5:0] | Output | p<n>_axi_st_clk |
Indicates the LTSSM state:
|