GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.14. Miscellaneous Signals

Table 56.  Miscellaneous Signalsn = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
Signal Name Direction Clock Domain Description
p<n>_ss_app_serr Output p<n>_axi_st_clk

Indicates System Error is detected.

In TLP Bypass mode indicates physical, data link, and transaction layer error detected by the PCIe* Hard IP.

p<n>_ss_app_dlup Output p<n>_axi_st_clk

When asserted, this signal indicates Data Link Layer is up.

p<n>_ss_app_linkup Output p<n>_axi_st_clk

When asserted, this signal indicates the link is up.

p<n>_ss_app_int_status Output p<n>_axi_st_clk

This signal drives legacy interrupts to the Application Layer. The source of the interrupt is logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.

Note: Applicable only in Root Port Mode.
p<n>_ss_app_surprise_down_err Output Async

Indicates that a surprise down event is occurring in the PCIe* Hard IP controller. Applicable for Downstream Port mode only.

p<n>_ss_app_ltssmstate[5:0] Output p<n>_axi_st_clk
Indicates the LTSSM state:
  • 6'h00: S_DETECT_QUIET
  • 6'h01: S_DETECT_ACT
  • 6'h02: S_POLL_ACTIVE
  • 6'h03: S_POLL_COMPLIANCE
  • 6'h04: S_POLL_CONFIG
  • 6'h05: S_PRE_DETECT_QUIET
  • 6'h06: S_DETECT_WAIT
  • 6'h07: S_CFG_LINKWD_START
  • 6'h08: S_CFG_LINKWD_ACEPT
  • 6'h09: S_CFG_LANENUM_WAI
  • 6'h0A: S_CFG_LANENUM_ACEPT
  • 6'h0B: S_CFG_COMPLETE
  • 6'h0C: S_CFG_IDLE
  • 6'h0D: S_RCVRY_LOCK
  • 6'h0E: S_RCVRY_SPEED
  • 6'h0F: S_RCVRY_RCVRCFG
  • 6'h10: S_RCVRY_IDLE
  • 6'h11: S_L0
  • 6'h12: S_L0S
  • 6'h13: S_L123_SEND_EIDLE
  • 6'h14: S_L1_IDLE
  • 6'h15: S_L2_IDLE
  • 6'h16: S_L2_WAKE
  • 6'h17: S_DISABLED_ENTRY
  • 6'h18: S_DISABLED_IDLE
  • 6'h19: S_DISABLED
  • 6'h1A: S_LPBK_ENTRY
  • 6'h1B: S_LPBK_ACTIVE
  • 6'h1C: S_LPBK_EXIT
  • 6'h1D: S_LPBK_EXIT_TIMEOUT
  • 6'h1E: S_HOT_RESET_ENTRY
  • 6'h1F: S_HOT_RESET
  • 6'h20: S_RCVRY_EQ0
  • 6'h21: S_RCVRY_EQ1
  • 6'h22: S_RCVRY_EQ2
  • 6'h23: S_RCVRY_EQ3