GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.12.1. AXI-Lite Usage for TLP Bypass Mode

The majority of the PCIe* standard registers are implemented in the user’s logic outside of the GTS AXI Streaming IP. However, the following registers remain inside the Agilex™ 5 PCIe* Hard IP:
  • Power management capability
  • PCI Express* capability
  • Secondary PCI Express* capability
  • Data link feature extended capability
  • Physical layer 16.0 GT/s extended capability
  • Lane margining at the receiver extended capability
  • Advanced error reporting capability

The application can only access PCIe* controller registers through the AXI-Lite interface.

Table 23.  Capability Registers to be updated by the Application Logic via the Control and Status Register Responder Interface
Capability Description
Power Management Capability Needed to write back for triggering a PCI-PM entry.
PCI Express Capability

All the PCIe* capabilities, control, and status registers are for configuring the device.

Write-back is required.

Secondary PCI Express Capability Secondary PCIe* Capability is required for configuring the device.
Data Link Feature Extended Capability Data Link Capability is device specific.
Physical Layer 16.0 GT/s Extended Capability Physical Layer 16G Capability is device specific.
Lane Margining at the Receiver Extended Capability Margining Extended Capability is device specific.
Advanced Error Reporting Capability Write-back to error status registers is required for TLP Bypass.