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1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters for E-Series FPGA
6. IP Parameters for D-Series FPGAs
7. Interfaces and Signals
8. Registers
9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP
3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Precision Time Measurement (PTM)
4.11. Single Root I/O Virtualization (SR-IOV)
4.12. Transaction Layer Packet (TLP) Bypass Mode
4.13. Scalable IOV
7.1. Overview
7.2. Clocks and Resets
7.3. AXI4-Stream Interfaces
7.4. Configuration Intercept Interface
7.5. Control Shadow Interface
7.6. Transmit Flow Control Credit Interface
7.7. Completion Timeout Interface
7.8. Control and Status Register Responder Interface
7.9. Function Level Reset Interface
7.10. TLP Bypass Error Reporting Interface
7.11. VF Error Flag Interface
7.12. Precision Time Measurement (PTM) Interface
7.13. Serial Data Signals
7.14. Miscellaneous Signals
8.6.1. VF PCI-Compatible Configuration Space Header Type0
8.6.2. VF PCI Express* Capability Structure
8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
8.6.4. VF Alternative Routing ID (ARI) Capability Structure
8.6.5. VF TLP Processing Hints (TPH) Capability Structure
8.6.6. VF Address Translation Services (ATS) Capability Structure
8.6.7. VF Access Control Services (ACS) Capability Structure
8.6.2.1. PCI Express* Capability List Register
8.6.2.2. PCI Express* Device Capabilities Register
8.6.2.3. PCI Express* Device Control and Status Register
8.6.2.4. Link Capabilities Register
8.6.2.5. Link Control and Status Register
8.6.2.6. PCI Express* Device Capabilities 2 Register
8.6.2.7. PCI Express* Device Control and Status 2 Register
8.6.2.8. Link Capabilities 2 Register
8.6.2.9. Link Control and Status 2 Register
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B. PIPE Mode Simulation
If you enable the Enable PIPE Mode Simulation parameter in the IP GUI, additional ports of the GTS AXI Streaming IP are exposed for simulation purposes only.
You must implement the following steps in your simulation files to enable the simulation mode.
- Connect the PIPE signal ports such as o_txpipe<n>_* and i_rxpipe<n>_* of the GTS AXI Streaming IP to the ports of Verification IP (VIP).
- Connect the reset signal of the VIP to p0_pin_perst_n_i/i_gpio_perst0_n ports of the GTS AXI Streaming IP.
- Connect o_pcs<n>_pipe_rst_n port of the GTS AXI Streaming IP to the VIP according to the chosen topology to generate PIPE reset to VIP as shown in the following table.
Table 98. o_pcs<n>_pipe_rst_n Signal Connections to VIP for PIPE Reset Mode PIPE Reset Signal Connections to VIP x8 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n, o_pcs2_pipe_rst_n, o_pcs3_pipe_rst_n, o_pcs4_pipe_rst_n, o_pcs5_pipe_rst_n, o_pcs6_pipe_rst_n, o_pcs7_pipe_rst_n x4 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n, o_pcs2_pipe_rst_n, o_pcs3_pipe_rst_n x2 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n x1 o_pcs0_pipe_rst_n - Connect the PIPE clock signal from the VIP to i_pcs0_pclk of the GTS AXI Streaming IP and ensure that the frequency of the clock is according to PCIe* speed rate.
- PCIe* 1.0: 125 MHz
- PCIe* 2.0: 250 MHz
- PCIe* 3.0: 500 MHz
- PCIe* 4.0: 1000 MHz
- Add the compile option +define+SM_PIPE_MODE to the simulation script. Examples for QuestaSim* are shown below:
- PIPE mode simulation:
USER_DEFINED_COMPILE_OPTIONS “+define+SM_PIPE_MODE”
- PIPE mode simulation along with FASTSIM:
USER_DEFINED_COMPILE_OPTIONS “+define+IP7521SERDES_UX_SIMSPEED +define+SM_PIPE_MODE"
Note: PIPE mode simulation is supported with and without FASTSIM mode. It is recommended that you enable both the PIPE mode and FASTSIM mode for shortest simulation time. - PIPE mode simulation: