GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

B. PIPE Mode Simulation

If you enable the Enable PIPE Mode Simulation parameter in the IP GUI, additional ports of the GTS AXI Streaming IP are exposed for simulation purposes only.

You must implement the following steps in your simulation files to enable the simulation mode.
  1. Connect the PIPE signal ports such as o_txpipe<n>_* and i_rxpipe<n>_* of the GTS AXI Streaming IP to the ports of Verification IP (VIP).
  2. Connect the reset signal of the VIP to p0_pin_perst_n_i/i_gpio_perst0_n ports of the GTS AXI Streaming IP.
  3. Connect o_pcs<n>_pipe_rst_n port of the GTS AXI Streaming IP to the VIP according to the chosen topology to generate PIPE reset to VIP as shown in the following table.
    Table 98.   o_pcs<n>_pipe_rst_n Signal Connections to VIP for PIPE Reset
    Mode PIPE Reset Signal Connections to VIP
    x8 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n, o_pcs2_pipe_rst_n, o_pcs3_pipe_rst_n, o_pcs4_pipe_rst_n, o_pcs5_pipe_rst_n, o_pcs6_pipe_rst_n, o_pcs7_pipe_rst_n
    x4 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n, o_pcs2_pipe_rst_n, o_pcs3_pipe_rst_n
    x2 o_pcs0_pipe_rst_n, o_pcs1_pipe_rst_n
    x1 o_pcs0_pipe_rst_n
  4. Connect the PIPE clock signal from the VIP to i_pcs0_pclk of the GTS AXI Streaming IP and ensure that the frequency of the clock is according to PCIe* speed rate.
    • PCIe* 1.0: 125 MHz
    • PCIe* 2.0: 250 MHz
    • PCIe* 3.0: 500 MHz
    • PCIe* 4.0: 1000 MHz
  5. Add the compile option +define+SM_PIPE_MODE to the simulation script. Examples for QuestaSim* are shown below:
    • PIPE mode simulation:
      USER_DEFINED_COMPILE_OPTIONS “+define+SM_PIPE_MODE”
    • PIPE mode simulation along with FASTSIM:
      USER_DEFINED_COMPILE_OPTIONS “+define+IP7521SERDES_UX_SIMSPEED +define+SM_PIPE_MODE"
    Note: PIPE mode simulation is supported with and without FASTSIM mode. It is recommended that you enable both the PIPE mode and FASTSIM mode for shortest simulation time.