Visible to Intel only — GUID: skm1696476863375
Ixiasoft
Visible to Intel only — GUID: skm1696476863375
Ixiasoft
4.8.5. Data and Header Packing Scheme
GTS AXI Streaming IP uses simple packing scheme with an inline header packet format where the header is presented on the same bus as data.
The simple packing scheme inserts a header starting at a fixed location. The header always starts from Byte Index 0. The rule of header starting on Byte Index 0 constrains the design to send one packet per cycle.
The PCIe* 4.0 x2/ PCIe* 4.0 x1 and all PCIe* 3.0 modes except PCIe* 3.0 x8 can take advantage of the 128-bit wide PLD interface. The 128-bit wide interface allows you to build design with smaller data path width. With the 128-bit interface, the header is transferred over two clock cycles provided tready signal is asserted.
The HIP IF Adaptor Tdata bus width varies based on link width and link speed to meet specific bandwidth requirement.
Mode | Data Width | PLD Clock Frequency (MHz) | Number of Streams |
---|---|---|---|
PCIe* 4.0 x8 | 512 | 500 | 1 |
PCIe* 4.0 x4/ PCIe* 3.0 x8 | 256 | 350 | 1 |
PCIe* 4.0 x2/ PCIe* 3.0 x4 | 128 | 300 | 1 |
PCIe* 4.0 x1/ PCIe* 3.0 x2/ PCIe* 3.0 x1 | 128 | 200 | 1 |