GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4. Hard IP Interface (IF) Adaptor

The PCIe* Hard IP (HIP) interfaces with the HIP IF Adaptor in the GTS AXI Streaming IP. The HIP IF adaptor acts as an interface between the HIP and the downstream logic. The HIP IF Adaptor provides a standardized interface to the downstream logic by performing the required width and format adaptation depending on the HIP’s AXI-Stream and user interfaces. The clock domain crossing module allows downstream logic to run at different frequencies.

Figure 14. Hard IP IF Adaptor