GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

2.4. Recommended FPGA Fabric Speed Grades

Table 5.   Agilex™ 5 Recommended FPGA Fabric Speed Grades for All AXI-Stream Width and Frequencies
Lane Rate Link Configuration Application Interface Data Width (in bits) Application Clock Frequency (MHz) Recommended FPGA Fabric Speed Grades
PCIe* 4.0 x8 512 500

-1

-2

450
400
350
300
250
200
x4 256 350

-1

-2

-3

-4

300
250
200
x2 128 300

-1

-2

-3

-4

250
200
x1 128

300

-1

-2

-3

-4

250

200

PCIe* 3.0 x8 256 350

-1

-2

-3

300
250
200
x4 128 300

-1

-2

-3

-4

-5

250
200

-1

-2

-3

-4

-5

-6

x2 128 300

-1

-2

-3

-4

-5

250
200

-1

-2

-3

-4

-5

-6

x1 128 300

-1

-2

-3

-4

-5

250
200

-1

-2

-3

-4

-5

-6

Attention: PCIe* 4.0 is only supported in -1, -2, -3, and -4 speed grade devices.
Note:
  1. Select the optimum PLD clock frequency to achieve maximum bandwidth. Refer to the Simple Packing Data Width and Optimum PLD Clock Frequency table for more details on the PLD clock frequencies.
  2. Higher than the optimum PLD clock frequency is allowed for some of the Hard IP modes above provided that the timing requirements can be met.