GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP

Following is the procedure to generate the GTS System PLL Clocks Intel® FPGA IP.

  1. Select GTS System PLL Clocks Intel® FPGA IP in the IP Catalog
  2. A New IP Variant window appears. Specify a top-level name for your new custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  3. Click Create. The parameter editor appears. Set the parameters as shown in the following table.
  4. Generate the GTS System PLL Clocks Intel® FPGA IP.
    1. Click Generate HDL.
    2. A Generation dialog box appears from the previous step. This allows you to generate a System PLL IP.
    3. Specify output file generation options, and then click Generate. The IP variation files are generated according to your specifications.
    4. Click Close. The parameter editor adds the top-level.ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
Table 8.  Setting GTS System PLL Clocks Intel® FPGA IP
Parameters Setting
Use case of System PLL TRANSCEIVER_USER_CASE
Mode of System PLL

Select the setting that match the PLD clock frequency in the GTS AXI Streaming IP.

  • PCIe* 4.0 x8: PCIE_FREQ_500/PCIE_FREQ_450/PCIE_FREQ_400/PCIE_FREQ_350//PCIE_FREQ_300/PCIE_FREQ_250/User_PCIE-based_Configuration_200.
  • PCIe* 4.0 x4: PCIE_FREQ_350/PCIE_FREQ_300/PCIE_FREQ_250/User_PCIE-based_Configuration_200.
  • PCIe* 3.0 x8: PCIE_FREQ_350//PCIE_FREQ_300/PCIE_FREQ_250/User_PCIE-based_Configuration_200.
  • PCIe* 4.0 x2/x1, PCIe* 3.0 x4/x2/x1: PCIE_FREQ_300/PCIE_FREQ_250/User_PCIE-based_Configuration_200.
Output frequency C0 Automatically set based on the Mode of System PLL setting.
Refclk frequency 100 MHz
Note:
  1. Refer to Implementing the GTS System PLL Clocks Intel® FPGA IP section in the GTS Transceiver PHY User Guide .
  2. PCIE_FREQ_300 denotes the PLD clock frequency of 300 MHz. This frequency needs to match the PLD clock frequency setting in the GTS AXI Streaming IP.
  3. The User_PCIE-based_Configuration_200 means to set Mode of System PLL to "User PCIe* -based Configuration" and Output frequency C0 to "200" in the GTS System PLL Clocks Intel® FPGA IP parameter editor GUI. This is needed when PLD clock frequency setting in the GTS AXI Streaming IP is set to 200 MHz.