GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.9.2. Function Level Reset Completion Interface

Table 51.  Function Level Reset Completion Interface
Signal Name Direction Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) Clock Domain Description
p<n>_app_ss_st_flrcmpl_tvalid Input EP p<n>_axi_lite_clk When asserted, it indicates a FLR request completed by application. The signal is valid for one clock cycle.
p<n>_app_ss_st_flrcmpl_tdata[19:0] Input EP p<n>_axi_lite_clk

Valid when p<n>_app_ss_st_flrcmpl_tvalid assert.

  • Bit[2:0]: The PF Number of FLR Completion
  • Bit[13:3]: Indicates child VF Number of parent PF indicated by PF Number
  • Bit[14]: Indicates completion is from Virtual Function implemented in controller’s physical function
  • Bit[19:15]: Reserved.

The figure below shows a timing diagram for function level reset completion from the application.

The first completion indicates FLR completion for Virtual Function = 0x10, and the p<n>_app_ss_st_flrcmpl_tdata[14] high indicates FLR completion from Virtual Function.

The second completion indicates FLR completion for Physical Function = 0x1.

The third completion indicates FLR completion for Virtual Function = 0x20, the p<n>_app_ss_st_flrcmpl_tdata[14] high indicates FLR completion from Virtual function.

The fourth completion indicates FLR completion for Physical Function =0x0.

Figure 60. Function Level Reset Completion Interface