Visible to Intel only — GUID: agl1711419037904
Ixiasoft
Visible to Intel only — GUID: agl1711419037904
Ixiasoft
7.9.2. Function Level Reset Completion Interface
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Clock Domain | Description |
---|---|---|---|---|
p<n>_app_ss_st_flrcmpl_tvalid | Input | EP | p<n>_axi_lite_clk | When asserted, it indicates a FLR request completed by application. The signal is valid for one clock cycle. |
p<n>_app_ss_st_flrcmpl_tdata[19:0] | Input | EP | p<n>_axi_lite_clk | Valid when p<n>_app_ss_st_flrcmpl_tvalid assert.
|
The figure below shows a timing diagram for function level reset completion from the application.
The first completion indicates FLR completion for Virtual Function = 0x10, and the p<n>_app_ss_st_flrcmpl_tdata[14] high indicates FLR completion from Virtual Function.
The second completion indicates FLR completion for Physical Function = 0x1.
The third completion indicates FLR completion for Virtual Function = 0x20, the p<n>_app_ss_st_flrcmpl_tdata[14] high indicates FLR completion from Virtual function.
The fourth completion indicates FLR completion for Physical Function =0x0.