GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.13. Serial Data Signals

The GTS AXI Streaming IP natively supports 1, 2, 4, or 8 PCIe* lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes. Refer to the Variables Used in the Bus Indices table for more details on bus indices.

The following table shows the signals of the serial interface of the GTS AXI Streaming IP.

Table 55.  Serial Data Signals
Signal Name Direction Clock Domain Description

tx_p_out[(b-1):0]

tx_n_out[(b-1):0]

Output

Transmit serial data outputs using the high-speed differential I/O standard.

rx_p_in[(b-1):0]

rx_n_in[(b-1):0]

Input

Receive serial data inputs using the high-speed differential I/O standard.