Visible to Intel only — GUID: mhm1710988775713
Ixiasoft
Visible to Intel only — GUID: mhm1710988775713
Ixiasoft
5.1. PCIe* Interfaces 0 Settings
Parameter | Value | Default Setting | Description | |
---|---|---|---|---|
PCIe* Interfaces 0 Settings | ||||
Hard IP Mode |
|
Gen3 x4 Interface 128 bit |
Selects the width of the data interface between the transaction layer and the application layer implemented in the PLD fabric, the lane data rate, and the lane rate. |
|
Enable TLP-bypass mode |
|
False | Enables the TLP Bypass feature. |
|
Port Mode |
When you set Enable TLP-bypass mode to false, the following values are available:
|
Native Endpoint | Selects the port mode. |
|
When you set Enable TLP-bypass mode to true, the following values are available:
|
Upstream Port | |||
Enable Debug Toolkit |
|
False | Enables the debug toolkit for the GTS AXI Streaming IP. |
|
PLD Clock Frequency |
|
300 MHz | Selects the PLD clock frequency.
Note:
|
|
Enable SRIS Mode |
|
False | Enables the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature. |
|
Enable PIPE Mode Simulation |
|
False | When selected, the PIPE mode simulation is enabled.
Note: This parameter is not supported for Quartus® Prime compilation.
The PIPE mode simulation is not supported for Questa* Intel® FPGA Edition. When running simulations with this parameter enabled, the following macro is required with the FASTSIM mode enabled: "+define+SM_PIPE_MODE" |
|
Enable CVP (Intel VSEC) |
|
False | Enables CvP for the device. | |
Optional Side Interfaces 0 | ||||
Port 0 Optional Side Interfaces 0 | ||||
Enable PCIe0 Control Shadow Interface |
|
False | Enables the Control Shadow Interface. Host write to specific PCIe* configuration space register's bit is indicated through this interface. |
|
Enable PCIe0 Completion Timeout Interface |
|
False | Enables the Completion Timeout Interface. Completion Timeout event is indicated through this interface. |
|
Enable PCIe0 Configuration Intercept Interface |
|
False | Enables the Configuration Intercept Interface. You can intercept PCIe* configuration cycles using this interface. |
|
When you set Enable PCIe0 Configuration Intercept Interface to true, the following options are available: |
PCIe0 CII REQ to ACK Latency Timeout value |
1–256 | 100 | Enables CII REQ to ACK Latency Timeout value (in clock cycles). The valid range is from 1 to 256. |
Enable Configuration Intercept Interface Monitor |
|
False | Enables the configuration intercept interface monitor. |