GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.5.1. Legacy Interrupt

You can enable the legacy interrupts by programming the Interrupt Disable bit (bit[10]) of the Configuration Space Command to 1'b0. When the legacy interrupts are enabled, the IP core emulates the INTx interrupts using virtual wires.

The legacy interrupts mimic the original PCI level-sensitive interrupts using virtual wire messages. The GTS AXI Streaming IP signals legacy interrupts on the PCIe* link using Message TLPs.

The term INTx refers collectively to the four legacy interrupts:
  • INTA#
  • INTB#
  • INTC#
  • INTD#

The application writes to control space register "LEGACY_INTERRUPT_CTRL" to generate Legacy Interrupt Message to HIP, to cause an Assert_INTx Message TLP to be generated by HIP and sent upstream. Another write to control space register causes a Deassert_INTx Message TLP to be generated and sent upstream.

To use legacy interrupts, you must clear the Interrupt Disable bit, which is bit 10 of the Command Register in the PCIe* configuration header. In addition, you must turn off the MSI Enable bit.

Your application needs to write "0x1" to LEGACY_INTERRUPT_CTRL through the AXI4-Lite Control and Status Register Responder interface to generate a Legacy Interrupt Message to HIP to cause an Assert_INTx Message TLP to be generated by HIP and sent upstream. This bit is expected to be cleared when the request is completed. Hence, your application is expected to need to read back the written register value to check if the request has been attended.

Similarly, your application needs to write "0x2" to LEGACY_INTERRUPT_CTRL through the AXI4-Lite Control and Status Register Responder interface to generate Legacy Interrupt Message to HIP to cause a Deassert_INTx Message TLP to be generated by HIP and sent upstream. This bit is expected to be cleared when the request is completed.

Figure 15. Generation of Assert and Deassert Messages through LEGACY_INTERRUPT_CTRL Control Space Register Timing Diagram