GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.4.1. Configuration Intercept Request Interface

The application logic detects the CFG request at the assertion of p0_ss_app_st_ciireq_tvalid on the Configuration Intercept Request Interface and uses the interface to:
  • Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first. This can be achieved by withholding the assertion of p0_app_ss_st_ciireq_tready.
  • Overwrite the data payload of a configuration write request. The application logic also overwrites the data payload of a configuration read completion TLP. This can be achieved by using the Configuration Intercept Response Interface.
Table 43.  Configuration Intercept Request Interfacen = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
Signal Name Direction Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) Clock Domain Description
p<n>_ss_app_st_ciireq_tvalid Output EP p<n>_axi_lite_clk

When asserted, indicates a valid CFG request cycle is waiting to be intercepted. Deasserted when p<n>_app_ss_st_ciireq_tready is asserted.

p<n>_app_ss_st_cciireq_tready Input EP p<n>_axi_lite_clk

The application asserts this signal for one clock to acknowledge p<n>_ss_app_st_ciireq_tvalid is seen by responder.

p<n>_ss_app_st_ciireq_tdata[71:0]

Output EP p<n>_axi_lite_clk
  • Bit [0]: The poisoned bit in the received TLP header on the CII.
  • Bit [4:1]: The first dword byte enable field in the received TLP header on the CII.
  • Bit [9:5]: Reserved.
  • Bit [12:10]: The PF number in the received TLP header on the CII.
  • Bit [23:13]: The child VF number of parent PF in the received TLP header on the CII.
  • Bit [24]: Indicates VF number is valid in the received TLP header on the CII.
  • Bit [25]: Indicates a configuration write request detected in the received TLP header on the CII. Also indicates that p<n>_ss_app_st_ciireq_tdata[67:36] is valid.
  • Bit [35:26]: The double word register address in the received TLP header on the CII.
  • Bit [67:36]: Received TLP payload data from the link partner to your application client. The data is in little endian format. The first received payload byte is in [43:36].
  • Bit [71:68]: Reserved.

The figure below shows the timing diagram for configuration write request indication to the application when the intercept feature is not enabled.

The first command is a config write to PF1 byte-1 and byte-0 at address = 0x200. The p<n>_ss_app_st_ciireq_tvalid is high for 1 clock cycle as the application is ready to accept the packet.

The second command is a full dword config write to VF=26 of PF5 at address = 0x3F0. As the application is not ready to accept the packet, the GTS AXI Streaming Intel® FPGA IP for PCI Express* holds the information until p<n>_app_ss_st_cciireq_tready is seen.

Figure 54. Configuration Intercept Request Interface