Visible to Intel only — GUID: mtf1711414771856
Ixiasoft
Visible to Intel only — GUID: mtf1711414771856
Ixiasoft
7.4.1. Configuration Intercept Request Interface
- Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first. This can be achieved by withholding the assertion of p0_app_ss_st_ciireq_tready.
- Overwrite the data payload of a configuration write request. The application logic also overwrites the data payload of a configuration read completion TLP. This can be achieved by using the Configuration Intercept Response Interface.
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Clock Domain | Description |
---|---|---|---|---|
p<n>_ss_app_st_ciireq_tvalid | Output | EP | p<n>_axi_lite_clk | When asserted, indicates a valid CFG request cycle is waiting to be intercepted. Deasserted when p<n>_app_ss_st_ciireq_tready is asserted. |
p<n>_app_ss_st_cciireq_tready | Input | EP | p<n>_axi_lite_clk | The application asserts this signal for one clock to acknowledge p<n>_ss_app_st_ciireq_tvalid is seen by responder. |
p<n>_ss_app_st_ciireq_tdata[71:0] |
Output | EP | p<n>_axi_lite_clk |
|
The figure below shows the timing diagram for configuration write request indication to the application when the intercept feature is not enabled.
The first command is a config write to PF1 byte-1 and byte-0 at address = 0x200. The p<n>_ss_app_st_ciireq_tvalid is high for 1 clock cycle as the application is ready to accept the packet.
The second command is a full dword config write to VF=26 of PF5 at address = 0x3F0. As the application is not ready to accept the packet, the GTS AXI Streaming Intel® FPGA IP for PCI Express* holds the information until p<n>_app_ss_st_cciireq_tready is seen.