GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 8/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters for E-Series FPGA 6. IP Parameters for D-Series FPGAs 7. Interfaces and Signals 8. Registers 9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Precision Time Measurement (PTM) 4.11. Single Root I/O Virtualization (SR-IOV) 4.12. Transaction Layer Packet (TLP) Bypass Mode 4.13. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.11. Single Root I/O Virtualization (SR-IOV) x
4.11.1. SR-IOV Implementation
4.12. Transaction Layer Packet (TLP) Bypass Mode x
4.12.1. AXI-Lite Usage for TLP Bypass Mode 4.12.2. Configuration TLP 4.12.3. Transmit Interface 4.12.4. Receive Interface 4.12.5. Malformed TLP 4.12.6. ECRC
5. IP Parameters for E-Series FPGA x
5.1. PCIe* Interfaces 0 Settings 5.2. AXI Interfaces 0 Settings 5.3. PCIe* 0 Settings
5.3. PCIe* 0 Settings x
5.3.1. PCIe* 0 Base Address Registers 5.3.2. PCIe* 0 Device Identification Registers 5.3.3. PCIe* 0 PCI Express* / PCI Capabilities
6. IP Parameters for D-Series FPGAs x
6.1. PCIe Interface 0 Settings 6.2. AXI Interfaces 0 Settings 6.3. PCIe0/PCIe1 Settings
6.3. PCIe0/PCIe1 Settings x
6.3.1. PCIe0/PCIe1 Base Address Registers 6.3.2. PCIe0/PCIe1 Device Identification Registers 6.3.3. PCIe0/PCIe1 PCI Express / PCI Capabilities
7. Interfaces and Signals x
7.1. Overview 7.2. Clocks and Resets 7.3. AXI4-Stream Interfaces 7.4. Configuration Intercept Interface 7.5. Control Shadow Interface 7.6. Transmit Flow Control Credit Interface 7.7. Completion Timeout Interface 7.8. Control and Status Register Responder Interface 7.9. Function Level Reset Interface 7.10. TLP Bypass Error Reporting Interface 7.11. VF Error Flag Interface 7.12. Precision Time Measurement (PTM) Interface 7.13. Serial Data Signals 7.14. Miscellaneous Signals
7.2. Clocks and Resets x
7.2.1. Interface Clock Signals 7.2.2. Interface Reset Signals Cold Reset Entry and Exit Sequence Warm Reset Entry and Exit Sequence User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence
7.3. AXI4-Stream Interfaces x
7.3.1. AXI4-Stream Receive (RX) Interface 7.3.2. AXI4-Stream Transmit (TX) Interface
7.4. Configuration Intercept Interface x
7.4.1. Configuration Intercept Request Interface 7.4.2. Configuration Intercept Response Interface
7.9. Function Level Reset Interface x
7.9.1. Function Level Reset Received Interface 7.9.2. Function Level Reset Completion Interface
8. Registers x
8.1. Register Address Map 8.2. PCI Express* Configuration Space 8.3. HIP Port and Status Registers 8.4. Soft Register Address Map 8.5. Indirect Register Access 8.6. Virtual Function (VF) PCI Express* Configuration Space 8.7. Intel-Defined VSEC Capability Register
8.2. PCI Express* Configuration Space x
8.2.1. PCI Express* Configuration Header Registers 8.2.2. PCI Express* Capability Structures 8.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
8.3. HIP Port and Status Registers x
8.3.1. Root Port Interrupt Registers 8.3.2. PTM Registers
8.4. Soft Register Address Map x
8.4.1. Control Registers 8.4.2. Debug Registers 8.4.3. Performance Monitor Registers
8.6. Virtual Function (VF) PCI Express* Configuration Space x
8.6.1. VF PCI-Compatible Configuration Space Header Type0 8.6.2. VF PCI Express* Capability Structure 8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 8.6.4. VF Alternative Routing ID (ARI) Capability Structure 8.6.5. VF TLP Processing Hints (TPH) Capability Structure 8.6.6. VF Address Translation Services (ATS) Capability Structure 8.6.7. VF Access Control Services (ACS) Capability Structure
8.6.1. VF PCI-Compatible Configuration Space Header Type0 x
8.6.1.1. Vendor ID and Device ID Registers 8.6.1.2. Command Registers 8.6.1.3. Status Registers 8.6.1.4. Revision ID and Class Code Register 8.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 8.6.1.6. Subsystem Vendor ID and Subsystem ID Register 8.6.1.7. Capabilities Pointer
8.6.2. VF PCI Express* Capability Structure x
8.6.2.1. PCI Express* Capability List Register 8.6.2.2. PCI Express* Device Capabilities Register 8.6.2.3. PCI Express* Device Control and Status Register 8.6.2.4. Link Capabilities Register 8.6.2.5. Link Control and Status Register 8.6.2.6. PCI Express* Device Capabilities 2 Register 8.6.2.7. PCI Express* Device Control and Status 2 Register 8.6.2.8. Link Capabilities 2 Register 8.6.2.9. Link Control and Status 2 Register
8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
8.6.3.1. MSI-X Control Register 8.6.3.2. MSI-X Table Offset Register 8.6.3.3. MSI-X Pending Bit Array Register
8.6.4. VF Alternative Routing ID (ARI) Capability Structure x
8.6.4.1. ARI Enhanced Capability Header Register 8.6.4.2. ARI Capability and Control Registers
8.6.5. VF TLP Processing Hints (TPH) Capability Structure x
8.6.5.1. TPH Requester Enhanced Capability Header 8.6.5.2. TPH Requester Capability Register 8.6.5.3. TPH Requester Control Register
8.6.6. VF Address Translation Services (ATS) Capability Structure x
8.6.6.1. ATS Enhanced Capability Header 8.6.6.2. ATS Capability Register and Control Register
8.6.7. VF Access Control Services (ACS) Capability Structure x
8.6.7.1. ACS Extended Capability Header 8.6.7.2. ACS Capability and Control Register 8.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters for E-Series FPGA
6. IP Parameters for D-Series FPGAs
7. Interfaces and Signals
8. Registers
9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation

7.2.2. Interface Reset Signals

Table 38.  Interface Reset Signalsn = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
Signal Name Direction Type Description
p<n>_subsystem_cold_rst_n Input

Can be implemented as synchronous or asynchronous reset.

GTS AXI Streaming IP global reset.

Resets sticky register bits.

Active low signal.

p<n>_subsystem_warm_rst_n

Input

Can be implemented as synchronous or asynchronous reset.

GTS AXI Streaming IP warm reset.

Does not reset sticky register bits.

Active low signal.
p<n>_subsystem_cold_rst_ack_n Output

Asynchronous handshake signal

Indicates that a cold reset action is completed by the GTS AXI Streaming IP.

p<n>_subsystem_warm_rst_ack_n Output

Asynchronous handshake signal

Indicates that a warm reset action is completed by the GTS AXI Streaming IP.

p<n>_axi_st_areset_n Input

The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of p<n>_axi_st_clk.

AXI-Stream main datapath reset.

Active low reset signal.

Used to reset the AXI-Stream datapath interface.

p<n>_axi_lite_areset_n Input The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of p<n>_axi_lite_clk.

AXI-Lite reset. Active low reset signal. Used to reset the AXI4-Lite Control and Status Register Responder interface.

p<n>_subsystem_rst_req Input

Asynchronous handshake signal

Reset entry indication from user reset control logic.

The GTS AXI Streaming IP queries the blocks in design upon receiving this request and sends an acknowledgment back when the block is ready for reset entry.

p<n>_subsystem_rst_rdy Output

Asynchronous handshake signal

Ready signal for the reset entry indication from the GTS AXI Streaming IP to the user reset control logic.

p<n>_initiate_warmrst_req Output

Asynchronous handshake signal

Warm Reset entry required indication from the IP core to user reset control logic.

The initiator block cannot issue new reset entry request until previous reset sequence (entire reset operation) is completed.
p<n>_initiate_rst_req_rdy Input

Asynchronous handshake signal

Indicates user reset control logic has accepted initiation request and starts issuing resets.
p0_pin_perst_n_i

p0_pin_perst_n_1_i

p1_pin_perst_n_i

Input

Asynchronous

This is an active low input for the PERST# function defined by the PCIe* specification. Connect PERST# to either one of the reset pins

You must assign a weak pull down to this pin in the Quartus® Prime software setting file. Example:

set_instance_assignment -name WEAK_PULL_DOWN ON -to p0_pin_perst_n_i

i_gpio_perst0_n

i_gpio_perst1_n

Input

Asynchronous

 Tie to logic high. i_gpio_perst1_n is only available in the Agilex™ 5 D-Series FPGAs.
p<n>_pin_perst_n Output

Asynchronous

 This is the PERST# indication for the HIP.
p<n>_reset_status_n Output

Synchronous to coreclkout_hip of HIP

Active low signal. When low, it indicates the HIP is in reset state.

The application logic can use this signal to drive its reset network.
ninit_done Input

Asynchronous

A "1" on this active low signal indicates that the FPGA device is not yet fully configured.

A "0" indicates the device has been configured and is in normal operating mode.
Note: You must implement the user reset sequencer in application user logic and follow the assertion and deassertion sequence for graceful entry and exit for each of the resets (cold, warm, etc.).

The following table indicates the signals or blocks used for each type of reset.

Table 39.  Signals or Blocks Used for Reset Type
Reset Type Signals/Blocks Under Reset
Cold Reset
  • subsystem_cold_rst_n and subsystem_warm_rst_n are asserted.
  • p0_axi_st_areset_n and p0_axi_lite_areset_n are asserted.
  • HIP undergoes reset.
Warm Reset (e.g., LTSSM Hot reset)
  • subsystem_warm_rst_n is asserted.
  • p0_axi_st_areset_n and p0_axi_lite_areset_n are asserted.
  • HIP undergoes reset too.
The expected reset isolation requirements for reset domain crossings are shown in the following table:
Table 40.  Reset Isolation Requirement for Reset Domain Crossings
  • No: No reset isolation required for Column->Row Reset Domain Crossing
  • Yes: Reset isolation required for Column->Row Reset Domain Crossing
  • N/A: Not applicable since same Reset Domain Crossing
Column: Source

Row: Destination

 Cold Reset HIP Reset Warm Reset AXI-Stream Reset AXI-Lite Reset
Cold Reset N/A No Yes No No
HIP Reset No N/A No No No
Warm Reset No No N/A No No
AXI-Stream Reset No No No N/A No
AXI-Lite Reset No No No No N/A
Note: In endpoint mode, the warm reset can be asserted without cold reset in scenarios such as LTSSM hot reset.

Cold Reset Entry and Exit Sequence

Following is the Cold Reset entry.
  1. Cold Reset is initiated by the deassertion of HIP input signal p<n>_pin_perst_n_i.
  2. HIP asserts pld_link_reset_req to the GTS AXI Streaming IP.
  3. The GTS AXI Streaming IP notifies the user reset controller by asserting p<n>_initiate_warmrst_req.
  4. The user reset controller asserts p0_subsystem_rst_req.
  5. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to the user reset controller.
  6. The user reset controller acknowledges to the GTS AXI Streaming IP that it is ready for reset by asserting p<n>_initiate_rst_req_rdy.
  7. The GTS AXI Streaming IP then asserts pld_warm_rst_rdy to HIP.
  8. HIP asserts p<n>_reset_status_n indicating the application logic needs to be in reset.
  9. User reset controller asserts p<n>_subsystem_cold_rst_n, p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Figure 44. Cold Reset Entry and Exit Sequence Timing Diagram

Warm Reset Entry and Exit Sequence

Warm Reset is initiated by the assertion of a HIP event, for example, hot reset. Following is the Warm Reset entry sequence.
  1. HIP asserts pld_link_reset_req to the GTS AXI Streaming IP.
  2. The GTS AXI Streaming IP notifies the user reset controller by asserting p<n>_initiate_warmrst_req.
  3. The user reset controller then asserts p<n>_subsystem_rst_req.
  4. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to the user reset controller.
  5. The user reset controller acknowledges to the subsystem that it is ready for reset by asserting p<n>_initiate_rst_req_rdy.
  6. The GTS AXI Streaming IP then asserts pld_warm_rst_rdy to HIP.
  7. HIP asserts p<n>_reset_status_n indicating the application logic needs to be in reset.
  8. The user reset controller asserts p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Note: The Warm Reset flow is similar to Cold Reset flow, with the exception that p<n>_pin_perst_n and p<n>_subsystem_cold_rst_n are not asserted for warm reset.
Figure 45. Warm Reset Entry and Exit Sequence Timing Diagram

User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence

  1. Cold Reset is initiated by the user reset controller by the assertion of the p<n>_subsystem_rst_req.
  2. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to user reset controller.
  3. User reset controller asserts p<n>_subsystem_cold_rst_n, p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Figure 46. User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence Timing Diagram

User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence

User reset controller triggered Warm Reset flow is the same as the user reset controller triggered Cold Reset flow, with the exception that the p<n>_subsystem_cold_rst_n is not asserted for this flow.

Figure 47. User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence Timing Diagram
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