Visible to Intel only — GUID: pbb1706171274136
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
Visible to Intel only — GUID: pbb1706171274136
Ixiasoft
4.4.3. Strict SFD/Preamble Checking
The Low Latency 40G Ethernet Intel® FPGA IP RX MAC checks all incoming packets for a correct Start byte (0xFB). If you turn on Enable Strict SFD check in the Low Latency 40G Ethernet Intel® FPGA IP parameter editor, you enable RX MAC to check the incoming preamble and SFD for the following values:
- SFD = 0xD5
- Preamble = 0x555555555555
The RX MAC checks one or both of these values depending on the values in bits [4:3] of the RXMAC_CONTROL register at offset 0x50A.
Enable Strict SFD check | 0x50A[4]: Preamble Check | 0x50A[3]: SFD Check | Fields Checked | Behavior if Check Fails |
---|---|---|---|---|
0 | Don't Care | Don't Care | Nothing | The IP passes the SOP EOP. |
1 | 0 | 0 | Nothing | |
0 | 1 | SFD | The IP drops the packet. | |
1 | 0 | Preamble | ||
1 | 1 | Preamble and SFD |