ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

Setting Up NativeLink and Simulation Settings

To set up the NativeLink and simulation settings, follow these steps:

  1. In the Quartus® Prime software, on the Tools menu, select Options.
  2. In the Options dialog box, under Category list, expand General and then select EDA Tool Options.
  3. In the EDA Tools Options window, follow the settings as shown in the following figure:
    Figure 31. EDA Tools Options Dialog Box


  4. In the Quartus® Prime software, on the Assignments menu, click Settings.
  5. In the Settings dialog box, under the Category list, expand EDA Tool Settings. Click Simulation.
  6. Enter the necessary NativeLink settings. The following figure shows an example settings. In this design example, a testbench (tb.v) is provided together with other supporting files.
    Figure 32. Simulation Dialog Box


    Figure 33. Test Benches Dialog Box


    Figure 34. Edit Test Bench Settings Dialog Box


  7. Run Analysis and Synthesis.
  8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTL Simulation.
    For a successful simulation, you may need to manually change alterapll.v to alterapll.vo in the auto-generated top_run_msim_rtl_verilog.do file.
  9. Before running the Fitter, ensure that the following settings are done in the Assignment Editor.
    • I/O Standard
    • Input Termination
    • Output Termination
    • DQ Group
    • Location assignment for strobe pin—this helps the Fitter to fit the related DQ pins in the appropriate l/O sub-banks. You can then back-annotate the locations if desired.
    The following figure shows an example setting in the Assignment Editor and the Pin Planner results:
    Figure 35. Assignment Editor Window


    Figure 36. Pin Planner


  10. Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the example design.
    Arria V device uses the PHYCLK by default.
    Figure 37. Design Example Clock Routing in Arria V Device
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