Visible to Intel only — GUID: sam1412661628761
Ixiasoft
Visible to Intel only — GUID: sam1412661628761
Ixiasoft
ALTDQ_DQS2 Termination Control Ports
Port name |
Type |
Width |
Description |
---|---|---|---|
parallelterminationcontrol_in[] | Input |
16 |
Controls the calibrated parallel termination ports of the input buffers. You must connect this port to the parallelterminationcontrol[15:0] port of the ALTOCT IP core. Ensure that the termination block located in the ALTOCT instance is assigned with the termination control block assignment. This port is supported in Arria V, Cyclone V, and Stratix V devices. |
seriesterminationcontrol_in[] | Input |
16 |
Controls the calibrated series termination ports of the output buffers. You must connect this port to the seriesterminationcontrol[15:0] port of the ALTOCT IP core. Ensure that the termination block located in the ALTOCT instance is assigned with the termination control block assignment. This port is supported in Arria V, Cyclone V, and Stratix V devices. |